FPGA Flow
Field-programmable gate arrays (FPGAs) are configurable integrated circuits that you can program to implement arbitrary circuit topologies. Classified as spatial compute architectures, FPGAs differ significantly from fixed Instruction Set Architecture (ISA) devices such as CPUs and GPUs. FPGAs offer a different set of optimization trade-offs from these traditional accelerator devices.
While you can compile DPC++ code for CPU, GPU or FPGA, the compiling process for FPGA development is somewhat different than that for CPU or GPU development.
The following table summarizes terminologies used in describing the FPGA flow:
Term | Definition |
|---|---|
Device code
| SYCL source code that executes on a SYCL device rather than the host. Device code is specified via lambda expression, functor, or kernel class. For example, kernel code.
|
Host code | SYCL source code that is compiled by the host compiler and executes on the host rather than the device.
|
Device image | The result of compiling the device code to a binary (or intermediate) representation. The device image is combined with the host binary, within a (fat) object or executable file. See
Compilation Flow Overview.
|
FPGA emulator image | The device image resulting from compiling for the FPGA emulator. See
FPGA Emulator |
FPGA early image | The device image resulting from the early image compilation stage. See
FPGA Optimization Report |
FPGA hardware image | The device image resulting from the hardware image compilation stage. See
FPGA Optimization Report and
FPGA Hardware.
|
You can also learn about programming for FPGAs in detail from the
Data Parallel C++
book available at
https://link.springer.com/chapter/10.1007/978-1-4842-5574-2_17.