sysmgr Address Map

System Manager core registers


Module Instance	Base Address	End Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D124FF`


Register	Offset	Width	Access	Reset Value	Description
`siliconid1`	`0x0`	`32`	`RO`	`0x00030000`	Silicon ID1 Register
`siliconid2`	`0x4`	`32`	`RO`	`0x00000000`	Silicon ID2 Register
`wddbg`	`0x8`	`32`	`RW`	`0x88080808`	L4 Watchdog Debug Register
`mpu_status`	`0x10`	`32`	`RO`	`0x00000000`	This is MPU control register
`sdmmc_l3master`	`0x2C`	`32`	`RW`	`0x0000F000`	Register for ACE-lite control -
`nand_l3master`	`0x34`	`32`	`RW`	`0x0C000C00`	NAND L3 Master AxCACHE Register
`usb0_l3master`	`0x38`	`32`	`RW`	`0x00003001`	USB L3 Master HPROT AHB-Lite Register
`usb1_l3master`	`0x3C`	`32`	`RW`	`0x0000F000`	Register for ACE-lite control - usb31_l3master
`tsn_global`	`0x40`	`32`	`RW`	`0x00000000`	TSN L3 Master AxCACHE Register
`tsn0`	`0x44`	`32`	`RW`	`0x00000003`	Control Register
`tsn1`	`0x48`	`32`	`RW`	`0x00000003`	Control Register
`tsn2`	`0x4C`	`32`	`RW`	`0x00000003`	Control Register
`tsn0_ace`	`0x50`	`32`	`RW`	`0x00000000`	The TSN0 ACE-lite control register
`tsn1_ace`	`0x54`	`32`	`RW`	`0x00000000`	The TSN1 ACE-lite control register
`tsn2_ace`	`0x58`	`32`	`RW`	`0x00000000`	The TSN2 ACE-lite control register
`fpga_bridge_ctrl`	`0x5C`	`32`	`RW`	`0x00000000`	fpga_bridge_ctrl register
`fpgaintf_en_1`	`0x68`	`32`	`RW`	`0x01010110`	FPGA interface Individual Enable Register
`fpgaintf_en_2`	`0x6C`	`32`	`RW`	`0x00000000`	FPGA interface Individual Enable Register
`fpgaintf_en_3`	`0x70`	`32`	`RW`	`0x00000000`	FPGA interface Individual Enable Register
`dmac0_l3master`	`0x74`	`32`	`RW`	`0x0000F000`	Register for ACE-lite control - dma_l3master
`etr_l3master`	`0x78`	`32`	`RW`	`0x0000F000`	Register for ACE-lite control - etr_l3master
`dmac1_l3master`	`0x7C`	`32`	`RW`	`0x0000F000`	Register for ACE-lite control - dma_l3master
`sec_ctrl_slt`	`0x80`	`32`	`RO`	`0x00000001`	This is the clock selection register. The APS oscillator selection is read only register. This value is driven from secure manager FS.
`osc_trim`	`0x84`	`32`	`RO`	`0x00000090`	This is the osc_trim register to show internal oscillator
`dmac0_ctrl_status_reg`	`0x88`	`32`	`RW`	`0x00000000`
`dmac1_ctrl_status_reg`	`0x8C`	`32`	`RW`	`0x00000000`
`ecc_intmask_value`	`0x90`	`32`	`RW`	`0x00000000`	ECC interrupt mask register. This is a read/write register.
`ecc_intmask_set`	`0x94`	`32`	`WO`	`0x00000000`	ECC interrupt mask Set register
`ecc_intmask_clr`	`0x98`	`32`	`WO`	`0x00000000`	ECC interrupt mask Clear register
`ecc_intstatus_serr`	`0x9C`	`32`	`RO`	`0x00000000`	ECC single bit error status of individual modules. A write to this register should return an error.
`ecc_intstatus_derr`	`0xA0`	`32`	`RO`	`0x00000000`	ECC double bit error status of individual modules. A write to this register should return an error.
`noc_timeout`	`0xC0`	`32`	`RW`	`0x00000000`
`noc_idlestatus`	`0xD4`	`32`	`RO`	`0x00000011`	Status of IDLE from the NOC masters. A 1 in the field means the specific master is idle.
`fpga2soc_ctrl`	`0xD8`	`32`	`RW`	`0x00000001`	Converts transactions from fpga2soc to non secure or allows both secure or non-secure transactions by fpga2soc.
`fpga_config`	`0xDC`	`32`	`RO`	`0x00000000`	FPGA configuration read only register
`gpo`	`0xE4`	`32`	`RW`	`0x00000000`	Provides a low-latency, low-performance, and simple way to drive general-purpose signals to the FPGA fabric
`gpi`	`0xE8`	`32`	`RO`	`0x00000000`	Provides a low-latency, low-performance, and simple way to read general-purpose signals driven from the FPGA fabric.
`mpu`	`0xF0`	`32`	`RW`	`0x00000000`	Provides a low-latency, low-performance, and simple way to read general-purpose signals driven from the FPGA fabric.
`sdm_hps_spare`	`0xF4`	`32`	`RW`	`0x00000000`	SDM to HPS spare signals are mapped to a system manager register. PSI side band signals will set these bits and HPS SW will clear this register
`hps_sdm_spare`	`0xF8`	`32`	`RW`	`0x00000000`	HPS to SDM spare signals are mapped to a system manager register.
`dfi_interface_cfg`	`0xFC`	`32`	`RW`	`0x00000000`	control bit used to set active DFI interface. 0 - DFI interface for HPNFC is active. 1 - DFI interface for SD is active. 2 - DFI interface fo XSPI is active.
`nand_dd_ctrl`	`0x100`	`32`	`RW`	`0x00C80010`
`nand_phy_ctrl_reg`	`0x104`	`32`	`RW`	`0x00004310`
`nand_phy_tsel_reg`	`0x108`	`32`	`RW`	`0x00000000`
`nand_phy_dq_timing_reg`	`0x10C`	`32`	`RW`	`0x00000002`
`phy_dqs_timing_reg`	`0x110`	`32`	`RW`	`0x00100004`
`nand_phy_gate_lpbk_ctrl_reg`	`0x114`	`32`	`RW`	`0x01A00000`
`nand_phy_dll_master_ctrl_reg`	`0x118`	`32`	`RW`	`0x00800000`
`nand_phy_dll_slave_ctrl_reg`	`0x11C`	`32`	`RW`	`0x00000000`
`nand_dd_default_setting_reg0`	`0x120`	`32`	`RW`	`0x00000000`	NAND Device Discovery Default Settings Register 1
`nand_dd_default_setting_reg1`	`0x124`	`32`	`RW`	`0x00000000`	NAND Device Discovery Default Settings Register 2
`nand_dd_status_reg`	`0x128`	`32`	`RO`	`0x00000000`	Nand Device DiscoveryStatus Register
`nand_dd_id_low_reg`	`0x12C`	`32`	`RO`	`0x00000000`	Device ID low Rgister
`nand_dd_id_high_reg`	`0x130`	`32`	`RO`	`0x00000000`	Device ID High Rgister
`nand_write_prot_en_reg`	`0x134`	`32`	`RW`	`0x00000000`	NAND write protection enable register
`sdmmc_cmd_queue_setting_reg`	`0x138`	`32`	`RW`	`0x00000640`	SDMMC Command queue setting register
`i3c_slv_pid_low`	`0x13C`	`32`	`RW`	`0x00000000`
`i3c_slv_pid_high`	`0x140`	`32`	`RW`	`0x00000000`
`i3c_slv_ctrl_0`	`0x144`	`32`	`RW`	`0x00000000`
`i3c_slv_ctrl_1`	`0x148`	`32`	`RW`	`0x00000000`
`f2s_bridge_ctrl`	`0x14C`	`32`	`RW`	`0x00000002`	f2s bridge control register
`dma_tbu_stash_ctrl_reg_0_dma0`	`0x150`	`32`	`RW`	`0x00000000`
`dma_tbu_stash_ctrl_reg_0_dma1`	`0x154`	`32`	`RW`	`0x00000000`
`sdm_tbu_stash_ctrl_reg_1_sdm`	`0x158`	`32`	`RW`	`0x00000000`
`io_tbu_stash_ctrl_reg_2_usb2`	`0x15C`	`32`	`RW`	`0x00000000`
`io_tbu_stash_ctrl_reg_2_usb3`	`0x160`	`32`	`RW`	`0x00000000`
`io_tbu_stash_ctrl_reg_2_sdmmc`	`0x164`	`32`	`RW`	`0x00000000`
`io_tbu_stash_ctrl_reg_2_nand`	`0x168`	`32`	`RW`	`0x00000000`
`io_tbu_stash_ctrl_reg_2_etr`	`0x16C`	`32`	`RW`	`0x00000000`
`tsn_tbu_stash_ctrl_reg_3_tsn0`	`0x170`	`32`	`RW`	`0x00000000`
`tsn_tbu_stash_ctrl_reg_3_tsn1`	`0x174`	`32`	`RW`	`0x00000000`
`tsn_tbu_stash_ctrl_reg_3_tsn2`	`0x178`	`32`	`RW`	`0x00000000`
`dma_tbu_stream_ctrl_reg_0_dma0`	`0x17C`	`32`	`RW`	`0x00000030`
`dma_tbu_stream_ctrl_reg_0_dma1`	`0x180`	`32`	`RW`	`0x00000030`
`sdm_tbu_stream_ctrl_reg_1_sdm`	`0x184`	`32`	`RW`	`0x00000033`
`io_tbu_stream_ctrl_reg_2_usb2`	`0x188`	`32`	`RW`	`0x00000030`
`io_tbu_stream_ctrl_reg_2_usb3`	`0x18C`	`32`	`RW`	`0x00000030`	for future use
`io_tbu_stream_ctrl_reg_2_sdmmc`	`0x190`	`32`	`RW`	`0x00000030`
`io_tbu_stream_ctrl_reg_2_nand`	`0x194`	`32`	`RW`	`0x00000030`
`io_tbu_stream_ctrl_reg_2_etr`	`0x198`	`32`	`RW`	`0x00000030`
`tsn_tbu_stream_ctrl_reg_3_tsn0`	`0x19C`	`32`	`RW`	`0x00000030`
`tsn_tbu_stream_ctrl_reg_3_tsn1`	`0x1A0`	`32`	`RW`	`0x00000030`
`tsn_tbu_stream_ctrl_reg_3_tsn2`	`0x1A4`	`32`	`RW`	`0x00000030`
`dma_tbu_stream_id_Ax_reg_0_dma0`	`0x1A8`	`32`	`RW`	`0x00000000`
`dma_tbu_stream_id_Ax_reg_0_dma1`	`0x1AC`	`32`	`RW`	`0x00000000`
`sdm_tbu_stream_id_Ax_reg_1_sdm`	`0x1B0`	`32`	`RW`	`0x00000000`
`io_tbu_stream_id_Ax_reg_2_usb2`	`0x1B4`	`32`	`RW`	`0x00000000`
`io_tbu_stream_id_Ax_reg_2_usb3`	`0x1B8`	`32`	`RW`	`0x00000000`
`io_tbu_stream_id_Ax_reg_2_sdmmc`	`0x1BC`	`32`	`RW`	`0x00000000`
`io_tbu_stream_id_Ax_reg_2_nand`	`0x1C0`	`32`	`RW`	`0x00000000`
`io_tbu_stream_id_Ax_reg_2_etr`	`0x1C4`	`32`	`RW`	`0x00000000`
`tsn_tbu_stream_id_Ax_reg_3_tsn0`	`0x1C8`	`32`	`RW`	`0x00000000`
`tsn_tbu_stream_id_Ax_reg_3_tsn1`	`0x1CC`	`32`	`RW`	`0x00000000`
`tsn_tbu_stream_id_Ax_reg_3_tsn2`	`0x1D0`	`32`	`RW`	`0x00000000`
`usb3_misc_ctrl_reg0`	`0x1F0`	`32`	`RW`	`0x07C00C11`
`usb3_misc_ctrl_reg1`	`0x1F4`	`32`	`RW`	`0x00000000`
`boot_scratch_cold0`	`0x200`	`32`	`RW`	`0x00000000`	Boot scratch register 0
`boot_scratch_cold1`	`0x204`	`32`	`RW`	`0x00000000`	Boot scratch register 1
`boot_scratch_cold2`	`0x208`	`32`	`RW`	`0x00000000`	Boot scratch register 2
`boot_scratch_cold3`	`0x20C`	`32`	`RW`	`0x00000000`	Boot scratch register 3
`boot_scratch_cold4`	`0x210`	`32`	`RW`	`0x00000000`	Boot scratch register 4
`boot_scratch_cold5`	`0x214`	`32`	`RW`	`0x00000000`	Boot scratch register 5
`boot_scratch_cold6`	`0x218`	`32`	`RW`	`0x00000000`	Boot scratch register 6
`boot_scratch_cold7`	`0x21C`	`32`	`RW`	`0x00000000`	Boot scratch register 7
`boot_scratch_cold8`	`0x220`	`32`	`RW`	`0x00000000`	Boot scratch register 8
`boot_scratch_cold9`	`0x224`	`32`	`RW`	`0x00000000`	Boot scratch register 9
`mpfe_config`	`0x228`	`32`	`RW`	`0x00000038`	mpfe_config
`mpfe_status`	`0x22C`	`32`	`RO`	`0x00000000`	mpfe_status
`boot_scratch_warm0`	`0x230`	`32`	`RW`	`0x00000000`	Boot scratch register 0
`boot_scratch_warm1`	`0x234`	`32`	`RW`	`0x00000000`	Boot scratch register 1
`boot_scratch_warm2`	`0x238`	`32`	`RW`	`0x00000000`	Boot scratch register 2
`boot_scratch_warm3`	`0x23C`	`32`	`RW`	`0x00000000`	Boot scratch register 3
`boot_scratch_warm4`	`0x240`	`32`	`RW`	`0x00000000`	Boot scratch register 4
`boot_scratch_warm5`	`0x244`	`32`	`RW`	`0x00000000`	Boot scratch register 5
`boot_scratch_warm6`	`0x248`	`32`	`RW`	`0x00000000`	Boot scratch register 6
`boot_scratch_warm7`	`0x24C`	`32`	`RW`	`0x00000000`	Boot scratch register 7
`boot_scratch_warm8`	`0x250`	`32`	`RW`	`0x00000000`	Boot scratch register 8
`boot_scratch_warm9`	`0x254`	`32`	`RW`	`0x00000000`	Boot scratch register 9
`boot_scratch_por0`	`0x258`	`32`	`RW`	`0x00000000`	Boot scratch register 0
`boot_scratch_por1`	`0x25C`	`32`	`RW`	`0x00000000`	Boot scratch register 1
`boot_scratch_por2`	`0x260`	`32`	`RW`	`0x00000000`	Boot scratch register 2
`boot_scratch_por3`	`0x264`	`32`	`RW`	`0x00000000`	Boot scratch register 3
`boot_scratch_por4`	`0x268`	`32`	`RW`	`0x00000000`	Boot scratch register 4
`boot_scratch_por5`	`0x26C`	`32`	`RW`	`0x00000000`	Boot scratch register 5
`boot_scratch_por6`	`0x270`	`32`	`RW`	`0x00000000`	Boot scratch register 6
`boot_scratch_por7`	`0x274`	`32`	`RW`	`0x00000000`	Boot scratch register 7
`boot_scratch_por8`	`0x278`	`32`	`RW`	`0x00000000`	Boot scratch register 8
`boot_scratch_por9`	`0x27C`	`32`	`RW`	`0x00000000`	Boot scratch register 9
`sdm_be_awaddr_remap`	`0x280`	`32`	`RW`	`0x00000000`
`sdm_be_araddr_remap`	`0x284`	`32`	`RW`	`0x00000000`