wddbg 

         Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These control registers are used to drive the pause input signal of the L4 watchdogs. Note that the watchdogs built into the MPU automatically are paused when their associated CPU enters debug mode. Only reset by a cold reset.
Module Instance Base Address Register Address
i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000 0x10D12000 0x10D12008

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

mode_4

RW 0x8

mode_3

RW 0x8

Reserved_3

RO 0x0

mode_2

RW 0x8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_2

RO 0x0

mode_1

RW 0x8

Reserved_1

RO 0x0

mode_0

RW 0x8

wddbg Fields

Bit Name Description Access Reset
31:28 mode_4 
Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
Value Description
0xf MODE_3_PAUSE_FOR_ANY_CPU
0x0 MODE_3_DONT_PAUSE
0x1 MODE_3_PAUSE_FOR_CPU0
0x2 MODE_3_PAUSE_FOR_CPU1
0x4 MODE_3_PAUSE_FOR_CPU2
0x8 MODE_3_PAUSE_FOR_CPU3
RW 0x8
27:24 mode_3 
Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
Value Description
0xf MODE_3_PAUSE_FOR_ANY_CPU
0x0 MODE_3_DONT_PAUSE
0x1 MODE_3_PAUSE_FOR_CPU0
0x2 MODE_3_PAUSE_FOR_CPU1
0x4 MODE_3_PAUSE_FOR_CPU2
0x8 MODE_3_PAUSE_FOR_CPU3
RW 0x8
23:20 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
19:16 mode_2 
Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
Value Description
0xf MODE_2_PAUSE_FOR_ANY_CPU
0x0 MODE_2_DONT_PAUSE
0x1 MODE_2_PAUSE_FOR_CPU0
0x2 MODE_2_PAUSE_FOR_CPU1
0x4 MODE_2_PAUSE_FOR_CPU2
0x8 MODE_2_PAUSE_FOR_CPU3
RW 0x8
15:12 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
11:8 mode_1 
Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
Value Description
0xf MODE_1_PAUSE_FOR_ANY_CPU
0x0 MODE_1_DONT_PAUSE
0x1 MODE_1_PAUSE_FOR_CPU0
0x2 MODE_1_PAUSE_FOR_CPU1
0x4 MODE_1_PAUSE_FOR_CPU2
0x8 MODE_1_PAUSE_FOR_CPU3
RW 0x8
7:4 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
3:0 mode_0 
Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
Value Description
0xf MODE_0_PAUSE_FOR_ANY_CPU
0x0 MODE_0_DONT_PAUSE
0x1 MODE_0_PAUSE_FOR_CPU0
0x2 MODE_0_PAUSE_FOR_CPU1
0x4 MODE_0_PAUSE_FOR_CPU2
0x8 MODE_0_PAUSE_FOR_CPU3
RW 0x8