fpga_bridge_ctrl 

         fpga_bridge_ctrl register
Module Instance Base Address Register Address
i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000 0x10D12000 0x10D1205C

Size: 32

Offset: 0x5C

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_2

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_2

RO 0x0

lwsoc2fpga_ready_latency_enable

RW 0x0

soc2fpga_ready_latency_enable

RW 0x0

fpga_bridge_ctrl Fields

Bit Name Description Access Reset
31:2 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
1 lwsoc2fpga_ready_latency_enable 

                     		
                     
                        RW
                     
                     
                        0x0
                     
                  

                  

                     0
                     
                        soc2fpga_ready_latency_enable
                     
                     
                        

                     		
                     
                        RW
                     
                     
                        0x0