f2s_bridge_ctrl

         f2s bridge control register


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D1214C`

Size: 32

Offset: 0x14C

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_3` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_3` `RO 0x0`													`f2soc_force_drain` `RW 0x0`	`f2soc_ready_latency_enable` `RW 0x1`	`f2soc_enable` `RW 0x0`

f2s_bridge_ctrl Fields


Bit	Name	Description	Access	Reset
31:3	`Reserved_3`	Reserved bitfield added by Magillem	`RO`	`0x0`
2	`f2soc_force_drain`		`RW`	`0x0`
1	`f2soc_ready_latency_enable`	0 = f2s bridge ready latency disable 1 = f2s bridge ready latency enabled	`RW`	`0x1`
0	`f2soc_enable`	0 = f2s bridge disable 1 = f2s bridge enabled	`RW`	`0x0`