nand_phy_ctrl_reg
Module Instance Base Address Register Address
i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000 0x10D12000 0x10D12104

Size: 32

Offset: 0x104

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_5

RO 0x0

pu_pd_polarity

RW 0x0

low_freq_sel

RW 0x0

Reserved_3

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_3

RO 0x0

sdr_dqs_value

RW 0x1

Reserved_2

RO 0x0

phony_dqs_timing

RW 0x31

Reserved_1

RO 0x0

ctrl_clkperiod_delay

RW 0x0

nand_phy_ctrl_reg Fields

Bit Name Description Access Reset
31:22 Reserved_5 
Reserved bitfield added by Magillem
 RO 0x0
21 pu_pd_polarity 
Defines the polarity of the ALE port that in SD works as pull-up/pull-down signal for bit 2 of the DATA
.•0 -ALE port is a copy of dfi_ale.
•1 -ALE port is inverted version of dfi_ale.
 RW 0x0
20 low_freq_sel 
If this field is set high the DFI interface is synchronous to the falling edge of the clock ie. the input signals are latched at the falling edge of the clk_ctrl and output signals are sync to falling edge of the clk_ctrl. Otherwise the interface is sync to the rising edge of the clk_ctrl.
 RW 0x0
19:15 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
14 sdr_dqs_value 
The value that should be driven on the DQS pin while SDR operations are in progress. Please note that in the DDR modes of operations, the command and address cycles are still in SDR mode. This field informs the PHY of the value to be driven onto the DQSbus during these SDR cycles.
 RW 0x1
13:10 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
9:4 phony_dqs_timing 
The timing of assertion of phony DQS to the data slices. If the extended_read_mode is disabled the value should be zero. If the extended_read_modeis enabled the value should match the width of the rebar pulse in terms of clock PHY clock cycles 
HPS System ManagerHASTemplate version 3.2Intel Confidential44NAND Controller Signal NameSystem Manager Bit?AttributeWrite set/clearReg RSTReset ValueDescriptionreduced by 1. e.g. if rebar pulse width is 4 clock cycles the value of this field should be 3
 RW 0x31
3:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 ctrl_clkperiod_delay 
Defines additional latency on the control signals ALE/CLE/ WE/RE/CE/WP
 RW 0x0