nand_dd_ctrl
Module Instance Base Address Register Address
i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000 0x10D12000 0x10D12100

Size: 32

Offset: 0x100

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rb_valid_time

RW 0xC8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_2

RO 0x0

discovery_ignore_crc

RW 0x1

Reserved_1

RO 0x0

discovery_inhibit

RW 0x0

nand_dd_ctrl Fields

Bit Name Description Access Reset
31:16 rb_valid_time 
The PHY initialization parameter for device discovery process. Value of this parameter should be calculated as: RB_VALID_TIME = Trb[us] * fsys [MHz], where: Trb - value of the "RB_valid_Vcc" time (from NAND flash device specification) fsys = 200MHz.
RW 0xC8
15:5 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
4 discovery_ignore_crc 
When tied to 1, the controller will ignore CRC checking after reading of parameter page during device discovery process.
RW 0x1
3:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 discovery_inhibit 
Bootstrap port to inhibit Controller from any initialization. Controller will not make device discovery process. This signal must be stable and have proper value by the time the Controller comes out of reset.
RW 0x0