i3c_slv_ctrl_0


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D12144`

Size: 32

Offset: 0x144

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`wakeup` `RO 0x0`	`i2c_glitch_filter_en` `RO 0x0`	`Reserved_4` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_4` `RO 0x0`								`pending_in` `RW 0x0`				`static_addr_en` `RW 0x0`	`act_mode` `RW 0x0`		`mode_i2c` `RW 0x0`

i3c_slv_ctrl_0 Fields


Bit	Name	Description	Access	Reset
31	`wakeup`		`RO`	`0x0`
30	`i2c_glitch_filter_en`		`RO`	`0x0`
29:8	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x0`
7:4	`pending_in`		`RW`	`0x0`
3	`static_addr_en`		`RW`	`0x0`
2:1	`act_mode`		`RW`	`0x0`
0	`mode_i2c`		`RW`	`0x0`