usb0_l3master 

         Controls the L3 master HPROT AHB-Lite signal.
These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation
All fields are reset by a cold or warm reset.
Module Instance Base Address Register Address
i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000 0x10D12000 0x10D12038

Size: 32

Offset: 0x38

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_5

RO 0x0

hauser22_13

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_4

RO 0x0

hauser7_6

RW 0x3

Reserved_3

RO 0x0

hauser_1

RW 0x0

hauser_0

RW 0x0

Reserved_1

RO 0x0

hprot

RW 0x1

usb0_l3master Fields

Bit Name Description Access Reset
31:26 Reserved_5 
Reserved bitfield added by Magillem
 RO 0x0
25:16 hauser22_13 
hauser[22:13]
 RW 0x0
15:14 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
13:12 hauser7_6 
hauser[7:6]
 RW 0x3
11:10 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
9 hauser_1 
hauser[1] secure
 RW 0x0
8 hauser_0 
hauser[0] allocate
 RW 0x0
7:4 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
3:0 hprot 
HPROT[0]: Opcode/Data
HPROT[1]: User/Privilege
HPROT[2]: Non-Bufferable/Bufferable
HPROT[3]: Non-Cacheable/Cacheable
 RW 0x1