tsn0

         Registers used by the TSN. All fields are reset by a cold or warm reset.


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D12044`

Size: 32

Offset: 0x44

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`axi_disable` `RW 0x0`	`sbd_data_endianness` `RW 0x0`	`Reserved_4` `RO 0x0`											`emac0_dbgbus_sel` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_3` `RO 0x0`							`Reserved`	`Reserved_2` `RO 0x0`			`ppstrig_sel` `RW 0x0`	`Reserved_1` `RO 0x0`		`phy_intf_sel` `RW 0x3`

tsn0 Fields

Bit Name Description Access Reset

axi_disable

AXI Disable

RW

0x0

sbd_data_endianness

Specifies the endianness of the TSN DMA transfers.
The field array index corresponds to the TSN index.

Value	Description
0	little_endian
1	big_endian

RW

0x0

29:19

Reserved_4

Reserved bitfield added by Magillem

RO

0x0

18:16

emac0_dbgbus_sel

RW

0x0

15:9

Reserved_3

Reserved bitfield added by Magillem

RO

0x0

Reserved

reserved

RW

0x0

7:5

Reserved_2

Reserved bitfield added by Magillem

RO

0x0

ppstrig_sel

Value	Description
0	emac_ppstrig_i
1	1

RW

0x0

3:2

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

1:0

phy_intf_sel

phy_intf_sel
0: PHY_INTF_GMII
1: PHY_INTF_RGMII
2: Reserved
3: PHY_INTF_RESET

Value	Description
0	GMII
1	RGMII
2	Reserved
3	RESET

RW

0x3