usb3_misc_ctrl_reg0


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D121F0`

Size: 32

Offset: 0x1F0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`bigendian_gs` `RW 0x0`	`devspd_ovrd` `RW 0x0`				`bus_filter_bypass` `RW 0xF`				`fladj_30mhz_reg` `RW 0x20`						`port_perm_attach` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`port_perm_attach` `RW 0x0`	`port_overcurrent` `RW 0x0`		`reset_pulse_ovrd` `RW 0x0`	`xhc_bme` `RW 0x1`	`force_gen1_speed` `RW 0x1`	`u3_disable_port` `RW 0x0`	`u2_disable_port` `RW 0x0`	`num_u3_port` `RW 0x1`				`num_u2_port` `RW 0x1`

usb3_misc_ctrl_reg0 Fields


Bit	Name	Access	Reset
31	`bigendian_gs`	`RW`	`0x0`
30:27	`devspd_ovrd`	`RW`	`0x0`
26:23	`bus_filter_bypass`	`RW`	`0xF`
22:17	`fladj_30mhz_reg`	`RW`	`0x20`
16:15	`port_perm_attach`	`RW`	`0x0`
14:13	`port_overcurrent`	`RW`	`0x0`
12	`reset_pulse_ovrd`	`RW`	`0x0`
11	`xhc_bme`	`RW`	`0x1`
10	`force_gen1_speed`	`RW`	`0x1`
9	`u3_disable_port`	`RW`	`0x0`
8	`u2_disable_port`	`RW`	`0x0`
7:4	`num_u3_port`	`RW`	`0x1`
3:0	`num_u2_port`	`RW`	`0x1`