tsn_global

         Controls the L3 master ARCACHE and AWCACHE AXI signals.
These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation
All fields are reset by a cold or warm reset.


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D12040`

Size: 32

Offset: 0x40

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`															`ptp_clk_sel` `RW 0x0`

tsn_global Fields

Bit Name Description Access Reset

31:1

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

ptp_clk_sel

Selects the source of the PTP reference clock between tsn_ptp_clk from the Clock Manager or f2s_ptp_ref_clk from the FPGA Fabric.

Value	Description
0	tsn_ptp_clk
1	f2s_ptp_ref_clk

RW

0x0