sdm_be_araddr_remap
Module Instance Base Address Register Address
i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000 0x10D12000 0x10D12284

Size: 32

Offset: 0x284

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

val

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

val

RW 0x0

sdm_be_araddr_remap Fields

Bit Name Description Access Reset
31:0 val 

                     		
                     
                        RW
                     
                     
                        0x0