nand_phy_tsel_reg


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D12108`

Size: 32

Offset: 0x108

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_4` `RO 0x0`								`tsel_off_value_data` `RW 0x0`				`tsel_rd_value_data` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`tsel_off_value_dqs` `RW 0x0`				`tsel_rd_value_dqs` `RW 0x0`				`Reserved_0` `RO 0x0`

nand_phy_tsel_reg Fields


Bit	Name	Description	Access	Reset
31:24	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x0`
23:20	`tsel_off_value_data`	Termination select off value for the data	`RW`	`0x0`
19:16	`tsel_rd_value_data`	ermination select read value for the data	`RW`	`0x0`
15:12	`tsel_off_value_dqs`	Termination select off valuefor the data strobe	`RW`	`0x0`
11:8	`tsel_rd_value_dqs`	Termination select read value for the data strobe	`RW`	`0x0`
7:0	`Reserved_0`	Reserved bitfield added by Magillem	`RO`	`0x0`