sdm_hps_spare

         SDM to HPS spare signals are mapped to a system manager register. PSI side band signals will set these bits and HPS SW will clear this register


Module Instance	Base Address	Register Address
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`	`0x10D12000`	`0x10D120F4`

Size: 32

Offset: 0xF4

Access: RW

Access mode: PRIVILEGEMODE | SECURE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_12` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_12` `RO 0x0`				`bit_11` `RW 0x0`	`bit_10` `RW 0x0`	`bit_9` `RW 0x0`	`bit_8` `RW 0x0`	`bit_7` `RW 0x0`	`bit_6` `RW 0x0`	`bit_5` `RW 0x0`	`bit_4` `RW 0x0`	`bit_3` `RW 0x0`	`bit_2` `RW 0x0`	`bit_1` `RW 0x0`	`bit_0` `RW 0x0`

sdm_hps_spare Fields


Bit	Name	Description	Access	Reset
31:12	`Reserved_12`	Reserved bitfield added by Magillem	`RO`	`0x0`
11	`bit_11`		`RW`	`0x0`
10	`bit_10`		`RW`	`0x0`
9	`bit_9`		`RW`	`0x0`
8	`bit_8`		`RW`	`0x0`
7	`bit_7`		`RW`	`0x0`
6	`bit_6`		`RW`	`0x0`
5	`bit_5`		`RW`	`0x0`
4	`bit_4`		`RW`	`0x0`
3	`bit_3`		`RW`	`0x0`
2	`bit_2`		`RW`	`0x0`
1	`bit_1`		`RW`	`0x0`
0	`bit_0`		`RW`	`0x0`