sysmgr Summary

System Manager core registers

Base Address: 0x10D12000


Register Address Offset	Bit Fields
`i_sys_mgr__sysmgr_csr__10d12000__core__SEG_L4_SHR_SystemManager_0x0_0x1000`
`siliconid1` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`id` `RO 0x3`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rev` `RO 0x0`
`siliconid2` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsv` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsv` `RO 0x0`												`device_revision` `RO 0x0`
`wddbg` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`mode_4` `RW 0x8`				`mode_3` `RW 0x8`				`Reserved_3` `RO 0x0`				`mode_2` `RW 0x8`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`				`mode_1` `RW 0x8`				`Reserved_1` `RO 0x0`				`mode_0` `RW 0x8`
`mpu_status` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`											`uncorrerr` `RO 0x0`
`sdmmc_l3master` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`						`aruser` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ardomain` `RW 0x3`		`awdomain` `RW 0x3`		`Reserved_1` `RO 0x0`		`awuser` `RW 0x0`
`nand_l3master` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`arcache_0` `RW 0x0`				`ardomain` `RW 0x3`		`aruser` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`awcache_0` `RW 0x0`				`awdomain` `RW 0x3`		`awuser` `RW 0x0`
`usb0_l3master` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`						`hauser22_13` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`		`hauser7_6` `RW 0x3`		`Reserved_3` `RO 0x0`		`hauser_1` `RW 0x0`	`hauser_0` `RW 0x0`	`Reserved_1` `RO 0x0`				`hprot` `RW 0x1`
`usb1_l3master` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`						`aruser` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ardomain` `RW 0x3`		`awdomain` `RW 0x3`		`Reserved_1` `RO 0x0`		`awuser` `RW 0x0`
`tsn_global` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`ptp_clk_sel` `RW 0x0`
`tsn0` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`axi_disable` `RW 0x0`	`sbd_data_endianness` `RW 0x0`	`Reserved_4` `RO 0x0`											`emac0_dbgbus_sel` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`							`Reserved`	`Reserved_2` `RO 0x0`			`ppstrig_sel` `RW 0x0`	`Reserved_1` `RO 0x0`		`phy_intf_sel` `RW 0x3`
`tsn1` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`axi_disable` `RW 0x0`	`sbd_data_endianness` `RW 0x0`	`Reserved_4` `RO 0x0`											`emac1_dbgbus_sel` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`							`Reserved`	`Reserved_2` `RO 0x0`			`ppstrig_sel` `RW 0x0`	`Reserved_1` `RO 0x0`		`phy_intf_sel` `RW 0x3`
`tsn2` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`axi_disable` `RW 0x0`	`sbd_data_endianness` `RW 0x0`	`Reserved_4` `RO 0x0`											`emac2_dbgbus_sel` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`							`Reserved`	`Reserved_2` `RO 0x0`			`ppstrig_sel` `RW 0x0`	`Reserved_1` `RO 0x0`		`phy_intf_sel` `RW 0x3`
`tsn0_ace` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`		`awsid` `RW 0x0`										`Reserved_1` `RO 0x0`		`arsid` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`arsid` `RW 0x0`								`Reserved_0` `RO 0x0`
`tsn1_ace` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`		`awsid` `RW 0x0`										`Reserved_1` `RO 0x0`		`arsid` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`arsid` `RW 0x0`								`Reserved_0` `RO 0x0`
`tsn2_ace` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`		`awsid` `RW 0x0`										`Reserved_1` `RO 0x0`		`arsid` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`arsid` `RW 0x0`								`Reserved_0` `RO 0x0`
`fpga_bridge_ctrl` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`														`lwsoc2fpga_ready_latency_enable` `RW 0x0`	`soc2fpga_ready_latency_enable` `RW 0x0`
`fpgaintf_en_1` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`ctmtrigger` `RW 0x1`	`Reserved_4` `RO 0x0`							`stmevent` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`							`dbgapb` `RW 0x1`	`Reserved_2` `RO 0x0`			`traceout` `RW 0x1`	`Reserved_1` `RO 0x0`			`tracein` `RW 0x0`
`fpgaintf_en_2` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`							`spim_1` `RW 0x0`	`Reserved_3` `RO 0x0`							`spim_0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`sdmmc` `RW 0x0`	`Reserved_1` `RO 0x0`			`nand` `RW 0x0`	`Reserved_0` `RO 0x0`
`fpgaintf_en_3` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`															`tsn_2` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`tsn_1` `RW 0x0`	`Reserved_1` `RO 0x0`							`tsn_0` `RW 0x0`
`dmac0_l3master` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`						`aruser` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ardomain` `RW 0x3`		`awdomain` `RW 0x3`		`Reserved_1` `RO 0x0`		`awuser` `RW 0x0`
`etr_l3master` `0x120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`						`aruser` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ardomain` `RW 0x3`		`awdomain` `RW 0x3`		`Reserved_1` `RO 0x0`		`awuser` `RW 0x0`
`dmac1_l3master` `0x124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`						`aruser` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ardomain` `RW 0x3`		`awdomain` `RW 0x3`		`Reserved_1` `RO 0x0`		`awuser` `RW 0x0`
`sec_ctrl_slt` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`val` `RO 0x1`
`osc_trim` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`val` `RO 0x90`
`dmac0_ctrl_status_reg` `0x136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mode` `RW 0x0`
`dmac1_ctrl_status_reg` `0x140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mode` `RW 0x0`
`ecc_intmask_value` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_18` `RO 0x0`													`dma1` `RW 0x0`	`ddr1` `RW 0x0`	`ddr0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmcb` `RW 0x0`	`sdmmca` `RW 0x0`	`nand_rd` `RW 0x0`	`usb31_ram2` `RW 0x0`	`usb31_ram1` `RW 0x0`	`dma0` `RW 0x0`	`tsn2_tx` `RW 0x0`	`tsn2_rx` `RW 0x0`	`tsn1_tx` `RW 0x0`	`tsn1_rx` `RW 0x0`	`tsn0_tx` `RW 0x0`	`tsn0_rx` `RW 0x0`	`usb31_ram0` `RW 0x0`	`usb0` `RW 0x0`	`ocram` `RW 0x0`	`Reserved_0` `RO 0x0`
`ecc_intmask_set` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_18` `WO 0x0`													`dma1` `RW 0x0`	`ddr1` `RW 0x0`	`ddr0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmcb` `RW 0x0`	`sdmmca` `RW 0x0`	`nand_rd` `RW 0x0`	`usb31_ram2` `RW 0x0`	`usb31_ram1` `RW 0x0`	`dma0` `RW 0x0`	`tsn2_tx` `RW 0x0`	`tsn2_rx` `RW 0x0`	`tsn1_tx` `RW 0x0`	`tsn1_rx` `RW 0x0`	`tsn0_tx` `RW 0x0`	`tsn0_rx` `RW 0x0`	`usb31_ram0` `RW 0x0`	`usb0` `RW 0x0`	`ocram` `RW 0x0`	`Reserved_0` `WO 0x0`
`ecc_intmask_clr` `0x152` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_18` `WO 0x0`													`dma1` `RW 0x0`	`ddr1` `RW 0x0`	`ddr0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmcb` `RW 0x0`	`sdmmca` `RW 0x0`	`nand_rd` `RW 0x0`	`usb31_ram2` `RW 0x0`	`usb31_ram1` `RW 0x0`	`dma0` `RW 0x0`	`tsn2_tx` `RW 0x0`	`tsn2_rx` `RW 0x0`	`tsn1_tx` `RW 0x0`	`tsn1_rx` `RW 0x0`	`tsn0_tx` `RW 0x0`	`tsn0_rx` `RW 0x0`	`usb31_ram0` `RW 0x0`	`usb0` `RW 0x0`	`ocram` `RW 0x0`	`Reserved_0` `WO 0x0`
`ecc_intstatus_serr` `0x156` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_18` `RO 0x0`													`dma1` `RO 0x0`	`ddr1` `RO 0x0`	`ddr0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmcb` `RO 0x0`	`sdmmca` `RO 0x0`	`nand_rd` `RO 0x0`	`usb31_ram2` `RO 0x0`	`usb31_ram1` `RO 0x0`	`dma0` `RO 0x0`	`tsn2_tx` `RO 0x0`	`tsn2_rx` `RO 0x0`	`tsn1_tx` `RO 0x0`	`tsn1_rx` `RO 0x0`	`tsn0_tx` `RO 0x0`	`tsn0_rx` `RO 0x0`	`usb31_ram0` `RO 0x0`	`usb0` `RO 0x0`	`ocram` `RO 0x0`	`Reserved_0` `RO 0x0`
`ecc_intstatus_derr` `0x160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_18` `RO 0x0`													`dma1` `RO 0x0`	`ddr1` `RO 0x0`	`ddr0` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmcb` `RO 0x0`	`sdmmca` `RO 0x0`	`nand_rd` `RO 0x0`	`usb31_ram2` `RO 0x0`	`usb31_ram1` `RO 0x0`	`dma0` `RO 0x0`	`tsn2_tx` `RO 0x0`	`tsn2_rx` `RO 0x0`	`tsn1_tx` `RO 0x0`	`tsn1_rx` `RO 0x0`	`tsn0_tx` `RO 0x0`	`tsn0_rx` `RO 0x0`	`usb31_ram0` `RO 0x0`	`usb0` `RO 0x0`	`ocram` `RO 0x0`	`Reserved_0` `RO 0x0`
`noc_timeout` `0x192` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`en` `RW 0x0`
`noc_idlestatus` `0x212` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`											`lwsoc2fpga` `RO 0x1`	`Reserved_1` `RO 0x0`			`soc2fpga` `RO 0x1`
`fpga2soc_ctrl` `0x216` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`allow_secure` `RW 0x1`
`fpga_config` `0x220` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`														`early_usermode` `RO 0x0`	`fpga_complete` `RO 0x0`
`gpo` `0x228` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`gpi` `0x232` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RO 0x0`
`mpu` `0x240` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu_cfgsdisable` `RW 0x0`
`sdm_hps_spare` `0x244` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_12` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_12` `RO 0x0`				`bit_11` `RW 0x0`	`bit_10` `RW 0x0`	`bit_9` `RW 0x0`	`bit_8` `RW 0x0`	`bit_7` `RW 0x0`	`bit_6` `RW 0x0`	`bit_5` `RW 0x0`	`bit_4` `RW 0x0`	`bit_3` `RW 0x0`	`bit_2` `RW 0x0`	`bit_1` `RW 0x0`	`bit_0` `RW 0x0`
`hps_sdm_spare` `0x248` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`													`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`dfi_interface_cfg` `0x252` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`dfi_ctrl_sel` `RW 0x0`
`nand_dd_ctrl` `0x256` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rb_valid_time` `RW 0xC8`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`											`discovery_ignore_crc` `RW 0x1`	`Reserved_1` `RO 0x0`			`discovery_inhibit` `RW 0x0`
`nand_phy_ctrl_reg` `0x260` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`										`pu_pd_polarity` `RW 0x0`	`low_freq_sel` `RW 0x0`	`Reserved_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`	`sdr_dqs_value` `RW 0x1`	`Reserved_2` `RO 0x0`				`phony_dqs_timing` `RW 0x31`						`Reserved_1` `RO 0x0`			`ctrl_clkperiod_delay` `RW 0x0`
`nand_phy_tsel_reg` `0x264` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`								`tsel_off_value_data` `RW 0x0`				`tsel_rd_value_data` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`tsel_off_value_dqs` `RW 0x0`				`tsel_rd_value_dqs` `RW 0x0`				`Reserved_0` `RO 0x0`
`nand_phy_dq_timing_reg` `0x268` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`								`data_clkperiod_delay` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`data_select_tsel_start` `RW 0x0`				`data_select_tsel_end` `RW 0x0`				`Reserved_2` `RO 0x0`	`data_select_oe_start` `RW 0x0`			`Reserved_1` `RO 0x0`	`data_select_oe_end` `RW 0x2`
`phy_dqs_timing_reg` `0x272` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`								`dqs_clkperiod_delay` `RW 0x0`	`Reserved_6` `RO 0x0`		`use_phony_dqs` `RW 0x1`	`Reserved_5` `RO 0x0`			`phony_dqs_sel` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`dqs_select_tsel_start` `RW 0x0`				`dqs_select_tsel_end` `RW 0x0`				`dqs_select_oe_start` `RW 0x0`				`dqs_select_oe_end` `RW 0x4`
`nand_phy_gate_lpbk_ctrl_reg` `0x276` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`sync_method` `RW 0x0`	`sw_dqs_phase_bypass` `RW 0x0`	`en_sw_half_cycle` `RW 0x0`	`sw_half_cycle_shift` `RW 0x0`	`param_phase_detect_sel_oe` `RW 0x0`			`rd_del_sel` `RW 0x34`						`underrun_suppress` `RW 0x0`	`Reserved_8` `RO 0x0`	`rd_del_sel_empty` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`lpbk_err_check_timing` `RW 0x0`			`lpbk_fail_muxsel` `RW 0x0`	`loopback_control` `RW 0x0`		`lpbk_internal` `RW 0x0`	`lpbk_en` `RW 0x0`	`Reserved_2` `RO 0x0`		`gate_cfg_close` `RW 0x0`		`gate_cfg` `RW 0x0`
`nand_phy_dll_master_ctrl_reg` `0x280` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`								`param_dll_bypass_mode` `RW 0x1`	`param_phase_detect_sel` `RW 0x0`			`Reserved_2` `RO 0x0`	`param_dll_lock_num` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`param_dll_start_point` `RW 0x0`
`nand_phy_dll_slave_ctrl_reg` `0x284` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`								`clk_wrdqs_delay` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`clk_wr_delay` `RW 0x0`								`read_dqs_delay` `RW 0x0`
`nand_dd_default_setting_reg0` `0x288` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`dd_pages_per_block` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`dd_page_size` `RW 0x0`
`nand_dd_default_setting_reg1` `0x292` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`							`dd_ack` `RW 0x0`	`dd_lun_number` `RW 0x0`				`Reserved_2` `RO 0x0`	`dd_row_addr_width` `RW 0x0`		`dd_support_16_bit` `RW 0x0`
`nand_dd_status_reg` `0x296` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`												`dd_req` `RO 0x0`	`init_comp` `RO 0x0`	`init_fail` `RO 0x0`	`ctrl_busy` `RO 0x0`
`nand_dd_id_low_reg` `0x300` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`dd_id_value` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`dd_id_value` `RO 0x0`
`nand_dd_id_high_reg` `0x304` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`dd_id_value` `RO 0x0`
`nand_write_prot_en_reg` `0x308` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`											`wre_prot_en_1` `RW 0x0`	`Reserved_1` `RO 0x0`			`wre_prot_en_0` `RW 0x0`
`sdmmc_cmd_queue_setting_reg` `0x312` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`												`ITCMFMUL` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`	`ITCMFVAL` `RW 0x32`										`ITCFSEL` `RW 0x0`
`i3c_slv_pid_low` `0x316` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Val` `RW 0x0`
`i3c_slv_pid_high` `0x320` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Val` `RW 0x0`
`i3c_slv_ctrl_0` `0x324` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`wakeup` `RO 0x0`	`i2c_glitch_filter_en` `RO 0x0`	`Reserved_4` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_4` `RO 0x0`								`pending_in` `RW 0x0`				`static_addr_en` `RW 0x0`	`act_mode` `RW 0x0`		`mode_i2c` `RW 0x0`
`i3c_slv_ctrl_1` `0x328` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_6` `RO 0x0`	`static_addr` `RW 0x0`							`inst_id` `RW 0x0`				`Reserved_4` `RO 0x0`	`slv_clk_data_turn_time` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`	`slv_max_wr_speed` `RW 0x0`			`Reserved_2` `RO 0x0`	`slv_max_rd_speed` `RW 0x0`			`slv_dcr` `RW 0x0`
`f2s_bridge_ctrl` `0x332` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`													`f2soc_force_drain` `RW 0x0`	`f2soc_ready_latency_enable` `RW 0x1`	`f2soc_enable` `RW 0x0`
`dma_tbu_stash_ctrl_reg_0_dma0` `0x336` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`dma_tbu_stash_ctrl_reg_0_dma1` `0x340` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`sdm_tbu_stash_ctrl_reg_1_sdm` `0x344` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`io_tbu_stash_ctrl_reg_2_usb2` `0x348` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`io_tbu_stash_ctrl_reg_2_usb3` `0x352` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`io_tbu_stash_ctrl_reg_2_sdmmc` `0x356` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`io_tbu_stash_ctrl_reg_2_nand` `0x360` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`io_tbu_stash_ctrl_reg_2_etr` `0x364` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`tsn_tbu_stash_ctrl_reg_3_tsn0` `0x368` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`tsn_tbu_stash_ctrl_reg_3_tsn1` `0x372` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`tsn_tbu_stash_ctrl_reg_3_tsn2` `0x376` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_9` `RO 0x0`			`stashlpid_reg_val` `RW 0x0`					`Reserved_8` `RO 0x0`			`stashnid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_7` `RO 0x0`				`wsnoop_reg_val` `RW 0x0`				`rdoaminen_reg_val` `RW 0x0`		`wdoaminen_reg_val` `RW 0x0`		`rdoaminen_reg_ctrl` `RW 0x0`	`wdoaminen_reg_ctrl` `RW 0x0`	`stashlpiden_reg_ctrl` `RW 0x0`	`stashniden_reg_ctrl` `RW 0x0`
`dma_tbu_stream_ctrl_reg_0_dma0` `0x380` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`dma_tbu_stream_ctrl_reg_0_dma1` `0x384` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`sdm_tbu_stream_ctrl_reg_1_sdm` `0x388` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x1`	`wstreamiden_reg_ctrl` `RW 0x1`
`io_tbu_stream_ctrl_reg_2_usb2` `0x392` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`io_tbu_stream_ctrl_reg_2_usb3` `0x396` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`io_tbu_stream_ctrl_reg_2_sdmmc` `0x400` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`io_tbu_stream_ctrl_reg_2_nand` `0x404` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`io_tbu_stream_ctrl_reg_2_etr` `0x408` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`tsn_tbu_stream_ctrl_reg_3_tsn0` `0x412` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`tsn_tbu_stream_ctrl_reg_3_tsn1` `0x416` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`tsn_tbu_stream_ctrl_reg_3_tsn2` `0x420` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`spare_ctrl` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`spare_ctrl` `RW 0x0`										`rmmusecsid_reg_Val` `RW 0x1`	`wmmusecsid_reg_Val` `RW 0x1`	`rstreamsiden_reg_ctrl` `RW 0x0`	`wstreamsiden_reg_ctrl` `RW 0x0`	`rstreamiden_reg_ctrl` `RW 0x0`	`wstreamiden_reg_ctrl` `RW 0x0`
`dma_tbu_stream_id_Ax_reg_0_dma0` `0x424` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`dma_tbu_stream_id_Ax_reg_0_dma1` `0x428` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`sdm_tbu_stream_id_Ax_reg_1_sdm` `0x432` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`io_tbu_stream_id_Ax_reg_2_usb2` `0x436` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`io_tbu_stream_id_Ax_reg_2_usb3` `0x440` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`io_tbu_stream_id_Ax_reg_2_sdmmc` `0x444` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`io_tbu_stream_id_Ax_reg_2_nand` `0x448` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`io_tbu_stream_id_Ax_reg_2_etr` `0x452` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`tsn_tbu_stream_id_Ax_reg_3_tsn0` `0x456` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`tsn_tbu_stream_id_Ax_reg_3_tsn1` `0x460` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`tsn_tbu_stream_id_Ax_reg_3_tsn2` `0x464` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rmmusid_reg_val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`wmmusid_reg_val` `RW 0x0`
`usb3_misc_ctrl_reg0` `0x496` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`bigendian_gs` `RW 0x0`	`devspd_ovrd` `RW 0x0`				`bus_filter_bypass` `RW 0xF`				`fladj_30mhz_reg` `RW 0x20`						`port_perm_attach` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`port_perm_attach` `RW 0x0`	`port_overcurrent` `RW 0x0`		`reset_pulse_ovrd` `RW 0x0`	`xhc_bme` `RW 0x1`	`force_gen1_speed` `RW 0x1`	`u3_disable_port` `RW 0x0`	`u2_disable_port` `RW 0x0`	`num_u3_port` `RW 0x1`				`num_u2_port` `RW 0x1`
`usb3_misc_ctrl_reg1` `0x500` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold0` `0x512` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold1` `0x516` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold2` `0x520` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold3` `0x524` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold4` `0x528` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold5` `0x532` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold6` `0x536` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold7` `0x540` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold8` `0x544` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_cold9` `0x548` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`mpfe_config` `0x552` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`mpfe_config_spare` `RW 0x0`							`mpfe_lite_active` `RW 0x0`	`mpfe_f2sdram_active` `RW 0x0`	`mpfe_f2soc_active` `RW 0x0`	`mpfe_io96b_csr_clk_enable` `RW 0x1`	`mpfe_io96b_p1_clk_enable` `RW 0x1`	`mpfe_io96b_p0_clk_enable` `RW 0x1`	`mpfe_lite_intfcsel` `RW 0x0`	`f2sdram_intfcsel` `RW 0x0`	`f2soc_intfcsel` `RW 0x0`
`mpfe_status` `0x556` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`mpfeintfc_stat_spare_in` `RO 0x0`
`boot_scratch_warm0` `0x560` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_warm1` `0x564` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_warm2` `0x568` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_warm3` `0x572` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_warm4` `0x576` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_warm5` `0x580` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_warm6` `0x584` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_warm7` `0x588` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_warm8` `0x592` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_warm9` `0x596` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por0` `0x600` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por1` `0x604` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por2` `0x608` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por3` `0x612` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por4` `0x616` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por5` `0x620` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por6` `0x624` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por7` `0x628` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por8` `0x632` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`boot_scratch_por9` `0x636` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`sdm_be_awaddr_remap` `0x640` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`
`sdm_be_araddr_remap` `0x644` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`val` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`val` `RW 0x0`