IP Quality Metrics

Basics

Year IP was first released

2015

Earliest version of Intel Quartus Prime Design Software supported

16.1

Status

Production

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Simulation model for ModelSim*- Intel FPGA Edition

Timing and/or layout constraints

Documentation with revision control

Readme file

Y

Any additional customer deliverables provided with IP

N/A

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

N/A

Software drivers provided

N

Driver OS Support

N/A

Implementation

User interface

Avalon-ST (Datapath), Avalon-MM (Management)

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria 10

Industry standard compliance testing performed

N

If Yes, which tests?

N/A

If Yes, on which Intel FPGA devices?

N/A

If Yes, date performed

N/A

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA devices?

N/A

Interoperability reports available

N