Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683505
Date 1/27/2021
Public

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 20.3
IP Version 19.2.0
The Low Latency 100G Ethernet Intel FPGA IP core provides a design example which allows the user to:
  • Compile the design — to get an estimate IP core area and timing
  • Simulate the design — to verify the IP core functionality through simulation
  • Test the design on hardware — to test the design on the Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit
When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Steps for the Design Example

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