Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683505
Date 1/27/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Ethernet Toolkit Overview 4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Simulation Design Example Components 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling the Compilation-Only Project 1.7. Compiling and Configuring the Design Example in Hardware 1.8. Testing the Hardware Design Example
1.8. Testing the Hardware Design Example x
1.8.1. Testing the Hardware Design Example using Ethernet Link Inspector 1.8.2. Testing the Hardware Design Example using Ethernet Toolkit
2. Design Example Description x
2.1. Features 2.2. Design Example Behavior 2.3. Design Example Interface Signals 2.4. Design Example Registers
2.4. Design Example Registers x
2.4.1. Packet Generator Programming Sequence
3. Ethernet Toolkit Overview x
3.1. Features
1. Quick Start Guide
2. Design Example Description
3. Ethernet Toolkit Overview
4. Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

1.8.2. Testing the Hardware Design Example using Ethernet Toolkit

The Ethernet Toolkit (ETK) is a tool that continuously monitors an Ethernet link.

Available in the Intel® Quartus® Prime Pro Edition software version 19.4 and later, the toolkit features list follows the standalone Ethernet Link Inspector tool. The toolkit allows you to review the PHY status, PCS status, MAC status, RS-FEC status, and AN and LT status.

Follow these steps to test your design using the Ethernet Toolkit:

  1. In the IP tab of the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP, select Enable JTAG to Avalon Master Bridge.
  2. Compile your design.
  3. In the Intel® Quartus® Prime Pro Edition, click Tools > Programmer, click Hardware Setup.
    1. Select a programming hardware setup from currently selected hardware or add new hardware. Click Close.
    2. Click Start to program your design onto the device.
  4. Click Tools > System Debugging Tools > System Console to open a new system console window.
  5. In the System Console, follow these steps to open the Ethernet Toolkit:
    1. Select File > Load Design to load the programming file (*.sof). Click OK.
    2. In the Instances pane, select the Ethernet IP instance.
    3. In the Details pane, select Low Latency 100G EthernetIP Toolkit from the toolkit list.
      Figure 8. Ethernet Toolkit Explorer View
    4. In the General Commands tab, click Enable Serial PMA Loopback to establish the serial loopback.
    5. The Settings > Status tab provides link status enable and control options such as PCS and PHY Status, MAC settings, and AN and LT status. Click Start Reading All Status to start reading the link status.
    6. The Settings > Statistics Counters tab provides the example design packet generator settings, transmitter and receiver statistics.
      1. Deselect MAC Loopback Mode.
      2. Select your preferred Packet Generator Modes option.
      3. Click Start Packet Generator. This enables the packet generator.
      4. Click Start Reading Transmitter Statistics and Start Reading Receiver Statistics.
    7. The Settings > Testing Features tab provides a series of testing features to test the Ethernet link.
      1. Click Start PHY and Packet Generator Loopback Test to test your Ethernet link.
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