1.8.2. Testing the Hardware Design Example using Ethernet Toolkit
Available in the Intel® Quartus® Prime Pro Edition software version 19.4 and later, the toolkit features list follows the standalone Ethernet Link Inspector tool. The toolkit allows you to review the PHY status, PCS status, MAC status, RS-FEC status, and AN and LT status.
Follow these steps to test your design using the Ethernet Toolkit:
- In the IP tab of the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP, select Enable JTAG to Avalon Master Bridge.
- Compile your design.
- In the Intel® Quartus® Prime Pro Edition, click , click Hardware Setup.
- Select a programming hardware setup from currently selected hardware or add new hardware. Click Close.
- Click Start to program your design onto the device.
- Click to open a new system console window.
- In the
, follow these steps to open the Ethernet Toolkit:
- Select OK. to load the programming file (*.sof). Click
- In the Instances pane, select the Ethernet IP instance.
- In the Details pane, select Low Latency 100G EthernetIP Toolkit from the toolkit list.
Figure 8. Ethernet Toolkit Explorer View
- In the Enable Serial PMA Loopback to establish the serial loopback. tab, click
- The Start Reading All Status to start reading the link status. tab provides link status enable and control options such as PCS and PHY Status, MAC settings, and AN and LT status. Click
tab provides the example design packet generator settings, transmitter and receiver statistics.
- Deselect MAC Loopback Mode.
- Select your preferred Packet Generator Modes option.
- Click Start Packet Generator. This enables the packet generator.
- Click Start Reading Transmitter Statistics and Start Reading Receiver Statistics.
tab provides a series of testing features to test the Ethernet link.
- Click Start PHY and Packet Generator Loopback Test to test your Ethernet link.
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