Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
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2. Design Example Description
To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates a copy of the IP core; the testbench and hardware design example use this variation as the DUT. If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.
Section Content
Features
Design Example Behavior
Design Example Interface Signals
Design Example Registers