Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683505
Date 1/27/2021
Public

1.2. Simulation Design Example Components

Figure 3.  Low Latency 100G Ethernet Intel Stratix 10 FPGA Simulation Design Example Block Diagram
Table 1.   Low Latency 100G Ethernet Intel Stratix 10 FPGA Core Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

basic_avl_tb_top.v Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.

Testbench Scripts

run_vsim.do

The Mentor Graphics* ModelSim* script to run the testbench.

run_vcs.sh

The Synopsys* VCS* script to run the testbench.

run_vcsmx.sh

The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.

Note: Use run_vcsmx.sh when RS-FEC is enabled.
run_ncsim.sh

The Cadence NCSim script to run the testbench.

run_xcelium.sh The Cadence Xcelium* script to run the testbench.

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