Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683505
Date 1/27/2021

2.3. Design Example Interface Signals

The Low Latency 100G Ethernet Intel Stratix 10 FPGA testbench is self-contained and does not require you to drive any input signals.

Table 4.   Low Latency 100G Ethernet Intel Stratix 10 FPGA Hardware Design Example Interface Signals

Signal Direction Comments
clk50 Input Drive at 50 MHz. The intent is to drive this input from a 50 MHz oscillator on the board.
clk_ref_r Input Drive at 644.53125 or 322.265625 MHz.
cpu_resetn Input Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core.
tx_serial[3:0] Output Transceiver PHY output serial data.
rx_serial[3:0] Input Transceiver PHY input serial data.
user_led[7:0] Output Status signals. Currently the design example drives all of these signals to a constant value of 0.

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