Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683505
Date 1/27/2021
Public

1.1. Directory Structure

Figure 2.  Low Latency 100G Ethernet Intel Stratix 10 FPGA Design Example Directory Structure

The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design. The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench. The compilation-only design example is located in <design_example_dir>/compilation_test_design.

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