Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide
ID
683505
Date
1/27/2021
Public
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1.1. Directory Structure
1.2. Simulation Design Example Components
1.3. Hardware Design Example Components
1.4. Generating the Design
1.5. Simulating the Design Example Testbench
1.6. Compiling the Compilation-Only Project
1.7. Compiling and Configuring the Design Example in Hardware
1.8. Testing the Hardware Design Example
1.6. Compiling the Compilation-Only Project
To compile the compilation-only example project, follow these steps:
- Ensure compilation design example generation is complete.
- In the Intel® Quartus® Prime software, open the Intel® Quartus® Prime project <design_example_dir>/compilation_test_design/alt_e100s10.qpf.
- On the Processing menu, click Start Compilation.
After successful compilation, reports for timing and for resource utilization are available in your Intel® Quartus® Prime Pro Edition session.
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