Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683505
Date 1/27/2021
Public

1.7. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel® Stratix® 10 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/alt_e100s10.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in your <design_example_dir>/hardware_test_design/output_files directory. Follow these steps to program the hardware design example on the Intel® Stratix® 10 device:
    1. On the Tools menu, click Programmer.
    2. In the Programmer, click Hardware Setup.
    3. Select a programming device.
    4. Select and add the Intel® Stratix® 10 Transceiver Signal Integrity Development Kit to which your Intel® Quartus® Prime Pro Edition session can connect.
    5. Ensure that Mode is set to JTAG.
    6. Select the Intel® Stratix® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    7. In the row with your .sof, check the box for the .sof.
    8. Check the box in the Program/Configure column.
    9. Click Start.

Did you find the information on this page useful?

Characters remaining:

Feedback Message