F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
ID
792946
Date
3/31/2025
Public
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
Updated for: |
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Intel® Quartus® Prime Design Suite 24.3.1 |
IP Version 5.0.0 |
This user guide provides the features, architecture description, steps to instantiate, and guidelines about the F-Tile Low Latency 100G Ethernet Intel® FPGA IP for the Agilex™ 7 (F-Tile) devices.
Intended Audience
This document is intended for:
- Design architect to make IP selection during system level design planning phase
- Hardware designers when integrating the IP into their system level design
- Validation engineers during system level simulation and hardware validation phase
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