F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

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ID 792946
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support
3. Getting Started x
3.1. Installing and Licensing Intel FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel FPGA IP 3.5.3. Placement Settings for the 100G Ethernet Intel FPGA IP Core
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters x
4.1. Main Tab Options 4.2. Analog Parameter Tab Options
5. Functional Description x
5.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Functional Description x
5.1.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP TX MAC Datapath 5.1.2. 100 GbE TX PCS 5.1.3. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 100 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon Memory-Mapped Management Interface 7.6. Miscellaneous Status and Debug Signals 7.7. Flow Control Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. Statistics Registers
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

8.4.1. Statistics Registers

Table 24.  Transmit Side Statistics Registers The statistics counters do not reflect CRC errors the user forces by asserting the l1_tx_error signal.
Address Name Description Access
0x0 FRAGMENTS Number of transmitted frames undersized (less than 64 bytes) and reporting a CRC error (lower 32 bits). Applicable for RX only. RO
0x2 JABBERS Number of transmitted oversized frames reporting a CRC error (lower 32 bits). Applicable for RX only. RO
0x4 FCSERR Number of transmitted packets with FCS errors. (lower 32 bits). Applicable for RX only. RO
0x6 CRCERR_OKPKT Number of transmitted packets with a frame of length at least 64 reporting a FCS error (lower 32 bits). Applicable for RX only. RO
0x8 MCAST_DATA Number of errored multicast frames transmitted, excluding control frames. Applicable for RX only. RO
0xA BCAST_DATA_ERR Number of broadcast data frames transmitted, reporting a FCS error. Applicable for RX only. RO
0xC UCAST_DATA_ERR Number of errored unicast data frames transmitted reporting a FCS error. Applicable for RX only. RO
0xE MCAST_CTRL_ERR Number of errored multicast control frames transmitted, reporting a FCS error. Applicable for RX only. RO
0x10 BCAST_CTRL_ERR Number of errored broadcast control frames transmitted, reporting a FCS error. Applicable for RX only. RO
0x12 UCAST_CTRL_ERR Number of errored unicast control frames transmitted, reporting a FCS error. Applicable for RX only. RO
0x14 PAUSE_ERR Number of errored pause frames transmitted, reporting a FCS error. Applicable for RX only. RO
0x16 64B Number of 64-byte transmitted frames. RO
0x18 65to127B Number of transmitted frames between 65–127 bytes. RO
0x1A 128to255B Number of transmitted frames between 128–255 bytes. RO
0x1C 256to511B Number of transmitted frames between 256–511 bytes. RO
0x1E 512to1023B Number of transmitted frames between 512–1023 bytes. RO
0x20 1024to1518B Number of transmitted frames between 1024–1518 bytes. RO
0x22 1519toMAXB Number of transmitted frames of size between 1519 bytes and the number of bytes specified in the MAX_TX_SIZE_CONFIG register. RO
0x24 OVERSIZE Number of oversized frames (frames with more bytes than the number specified in the MAX_TX_SIZE_CONFIG register) transmitted. RO
0x26 MCAST_DATA_OK Number of valid multicast frames transmitted, excluding control frames. RO
0x28 BCAST_DATA_OK Number of valid broadcast frames transmitted, excluding control frames. RO
0x2A UCAST_DATA_OK Number of valid unicast frames transmitted, excluding control frames. RO
0x2C MCAST_CTRL_LO Number of valid multicast frames transmitted, excluding data frames. RO
0x2E BCAST_CTRL_LO Number of valid broadcast frames transmitted, excluding data frames. RO
0x30 UCAST_CTRL_LO Number of valid unicast frames transmitted, excluding data frames. RO
0x32 PAUSE Number of valid pause frames transmitted. RO
0x34 RNT Number of transmitted runt packets with length less than 64 bytes. RO
0x45 CNTR_CONFIG Bits[2:0]: Configuration of TX statistics counters:
  • Bit[2]: Shadow request (active high): When set to the value of 1, TX statistics collection is paused. The underlying counters continue to operate, but the readable values reflect a snapshot at the time the pause flag was activated. Write a 0 to release.
  • Bit[1]: Parity-error clear. When software sets this bit, the IP core clears the parity bit CNTR_TX_STATUS[0]. This bit (CNTR_TX_CONFIG[1]) is self-clearing.
  • Bit[0]: Software can set this bit to the value of 1 to reset all TX statistics registers at the same time. This bit is self-clearing.
 RW
0x846 CNTR_STATUS
  • Bit[1]: Indicates that the TX statistics registers are paused (while CNTR_CONFIG is asserted).
  • Bit[0]: Indicates the presence of at least one parity error in the TX statistics counters.
 RO
0x860 PayloadOctetsOK Number of transmitted payload bytes in frames with no FCS, undersized, oversized, or payload length errors. This is a 64-bits register. RO
0x862 FrameOctetsOK Number of transmitted or received bytes in frames with no FCS, undersized, oversized, or payload length errors. This is a 64-bits register. RO
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