F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

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ID 792946
Date 3/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support
3. Getting Started x
3.1. Installing and Licensing Intel FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel FPGA IP 3.5.3. Placement Settings for the 100G Ethernet Intel FPGA IP Core
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters x
4.1. Main Tab Options 4.2. Analog Parameter Tab Options
5. Functional Description x
5.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Functional Description x
5.1.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP TX MAC Datapath 5.1.2. 100 GbE TX PCS 5.1.3. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 100 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-Tile Low Latency 100G Ethernet Intel® FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon Memory-Mapped Management Interface 7.6. Miscellaneous Status and Debug Signals 7.7. Flow Control Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. Statistics Registers
1. About the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 100G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 100G Ethernet Intel® FPGA IP User Guide

7.9. Reset Signals

The IP core has three external hard reset inputs. Assert these resets for ten clk_status or until you observe the effect of their specific resets. Intel recommends that you perform a system reset before starting the IP core operation, preferably by asserting csr_rst_n signal. Asserting csr_rst_n returns control and status registers to their original value. Control and Status registers control three parallel soft resets. The six signals are summarized below.
Table 18.   Reset Signals
Signal Direction Description
i_rst_n Input Active low reset asynchronous signal. Do not deassert until the o_rst_ack_n deasserts.
  • Resets the TX interface, including the TX PCS.
  • Resets the RX interface, including the RX PCS.
  • Resets the TX PMA and TX EMIB.
  • Resets the RX PMA and RX EMIB.

This reset leads to the assertion of the o_rst_ack_n output signals.

o_rst_ack_n Output Active low asynchronous acknowledgement signal for i_rst_n.

Do not deassert i_rst_n until the o_rst_ack_n asserts.

i_tx_rst_n Input Active low reset asynchronous signal. Resets the TX datapath, including the TX PCS, TX MAC, TX PMA, and TX EMIB. Do not deassert until the o_tx_rst_ack_n asserts.
o_tx_rst_ack_n Output Active low asynchronous acknowledgement signal for the i_tx_rst_n. Do not deassert i_tx_rst_n until the o_tx_rst_ack_n asserts.
i_rx_rst_n Input

Active low hard reset signal. Resets the RX datapath, including the RX PCS, RX MAC, RX PMA, and RX EMIB. Do not deassert until the o_rx_rst_ack_n asserts.

o_rx_rst_ack_n Output Active low asynchronous acknowledgement signal for the i_rx_rst_n. Do not deassert i_rx_rst_n until the o_rx_rst_ack_n asserts.
i_reconfig_reset Input Active high reconfiguration reset signal. Reset the entire transceiver and Ethernet reconfiguration clock domain, including the soft registers (CSRs).

You must assert this reset after power-on or during the configuration. The reconfig_clk must be stable before deasserting this reset.

csr_rst_n Input Active low hard reset. Resets the MAC control, status, and statistics registers.
O_rx_rst_ack_n Output Acknowledge signal for i_rx_rst_n. Active low. You must not deassert i_rx_rst_n until o_rx_rst_n is asserted.
O_tx_lanes_stable Output Asserted when TX Datapath is ready to send data; deasserts when i_tx_rst_n or i_rst_n is asserted, Active high.
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