Thermal Design User Guide: MAX® 10 FPGA B610 Package

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ID 851247
Date 5/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines 2. MAX® 10 FPGA B610 Package Mechanical Construction 3. MAX® 10 FPGA B610 Package CTM Construction 4. Quartus Requirements and Power Estimation 5. General FPGA Thermal Design Considerations 6. Thermal Design Process 7. Thermal Solution Mechanical Design 8. Vendor References 9. Document Revision History for the MAX® 10 FPGA B610 Package Thermal Design User Guide A. Thermal Design Elements
1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines x
1.1. Thermal Design Requirements 1.2. Definitions of Thermal and Power Terms Used in this Document
2. MAX® 10 FPGA B610 Package Mechanical Construction x
2.1. Thermal Design Process Flow 2.2. Thermal Resistance Values Summary
3. MAX® 10 FPGA B610 Package CTM Construction x
3.1. CTM File Format 3.2. Thermal Modeling with the CTM 3.3. Obtaining the CTM
4. Quartus Requirements and Power Estimation x
4.1. Board Thermal Model 4.2. QPA Outputs
5. General FPGA Thermal Design Considerations x
5.1. FPGA Power Considerations 5.2. FPGA Maximum Allowed Power Dissipation 5.3. Static, Dynamic, and Standby Power
6. Thermal Design Process x
6.1. Package Heat Flow Path 6.2. Recommended Thermal Design Methodology
7. Thermal Solution Mechanical Design x
7.1. Mechanical Design 7.2. TIM2 Selection 7.3. Summary
7.1. Mechanical Design x
7.1.1. Bond Line Thickness (BLT) 7.1.2. Die Warpage 7.1.3. Package Loading 7.1.4. Recommended Pressure Variation Across the Package
7.2. TIM2 Selection x
7.2.1. Gap Pad TIMs 7.2.2. Gap Pad TIM Thermal Conductivity Data 7.2.3. Parametric Studies with Different TIM Materials
1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines
2. MAX® 10 FPGA B610 Package Mechanical Construction
3. MAX® 10 FPGA B610 Package CTM Construction
4. Quartus Requirements and Power Estimation
5. General FPGA Thermal Design Considerations
6. Thermal Design Process
7. Thermal Solution Mechanical Design
8. Vendor References
9. Document Revision History for the MAX® 10 FPGA B610 Package Thermal Design User Guide
A. Thermal Design Elements

2.2. Thermal Resistance Values Summary

The following table shows thermal resistance values determined for the MAX® 10 FPGA B610 package through detailed thermal simulations conducted under test board conditions compliant with JEDEC 51 standards. These values are for reference purposes to get early estimates of junction temperatures.

Table 2.   MAX® 10 FPGA B610 Package Thermal Resistance Values
Device Package type Package Type ӨJA(°C/W) Still Air ӨJA(°C/W) 100 ft/min ӨJA(°C/W) 200 ft/min ӨJA(°C/W) 400 ft/min ӨJC(°C/W) ӨJB(°C/W)
MAX® 10 Wire bond BGA 21.4 21.0 18.5 15.7 4.6 9.0
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