1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines
2. MAX® 10 FPGA B610 Package Mechanical Construction
3. MAX® 10 FPGA B610 Package CTM Construction
4. Quartus Requirements and Power Estimation
5. General FPGA Thermal Design Considerations
6. Thermal Design Process
7. Thermal Solution Mechanical Design
8. Vendor References
9. Document Revision History for the MAX® 10 FPGA B610 Package Thermal Design User Guide
A. Thermal Design Elements
7.2.2. Gap Pad TIM Thermal Conductivity Data
The following table provides data on some common types of commercially available thermal interface materials tested using ASTM D5470 standards. These conductivity values consider contact resistance between heat source and heat sink by measuring the temperature drop across the TIM and calculating it based on the provided heat input, thereby delivering an effective thermal conductivity value.
Parameter | GAP PADs |
---|---|
TIM k_eff [W/m-K] | 1-6 |
BLT [µm] | 800-1200 |