Thermal Design User Guide: MAX® 10 FPGA B610 Package

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ID 851247
Date 5/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines 2. MAX® 10 FPGA B610 Package Mechanical Construction 3. MAX® 10 FPGA B610 Package CTM Construction 4. Quartus Requirements and Power Estimation 5. General FPGA Thermal Design Considerations 6. Thermal Design Process 7. Thermal Solution Mechanical Design 8. Vendor References 9. Document Revision History for the MAX® 10 FPGA B610 Package Thermal Design User Guide A. Thermal Design Elements
1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines x
1.1. Thermal Design Requirements 1.2. Definitions of Thermal and Power Terms Used in this Document
2. MAX® 10 FPGA B610 Package Mechanical Construction x
2.1. Thermal Design Process Flow 2.2. Thermal Resistance Values Summary
3. MAX® 10 FPGA B610 Package CTM Construction x
3.1. CTM File Format 3.2. Thermal Modeling with the CTM 3.3. Obtaining the CTM
4. Quartus Requirements and Power Estimation x
4.1. Board Thermal Model 4.2. QPA Outputs
5. General FPGA Thermal Design Considerations x
5.1. FPGA Power Considerations 5.2. FPGA Maximum Allowed Power Dissipation 5.3. Static, Dynamic, and Standby Power
6. Thermal Design Process x
6.1. Package Heat Flow Path 6.2. Recommended Thermal Design Methodology
7. Thermal Solution Mechanical Design x
7.1. Mechanical Design 7.2. TIM2 Selection 7.3. Summary
7.1. Mechanical Design x
7.1.1. Bond Line Thickness (BLT) 7.1.2. Die Warpage 7.1.3. Package Loading 7.1.4. Recommended Pressure Variation Across the Package
7.2. TIM2 Selection x
7.2.1. Gap Pad TIMs 7.2.2. Gap Pad TIM Thermal Conductivity Data 7.2.3. Parametric Studies with Different TIM Materials
1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines
2. MAX® 10 FPGA B610 Package Mechanical Construction
3. MAX® 10 FPGA B610 Package CTM Construction
4. Quartus Requirements and Power Estimation
5. General FPGA Thermal Design Considerations
6. Thermal Design Process
7. Thermal Solution Mechanical Design
8. Vendor References
9. Document Revision History for the MAX® 10 FPGA B610 Package Thermal Design User Guide
A. Thermal Design Elements

7.2.3. Parametric Studies with Different TIM Materials

The sensitivity of various commonly used thermal interface materials (TIMs) was analyzed to evaluate their impact on the thermal performance of the MAX® 10 FPGA B610 package.

A baseline design was established using packages with heatsinks of different sizes, as shown in the table below. For each heatsink variant, a gap pad TIM with an effective thermal conductivity of 4 W/m-K and a bond line thickness (BLT) of 500µm was considered. This analysis did not account for changes in the spatial performance of TIM2. The following figure illustrates the increase in junction temperature for different designs as TIM conductivity varied from 1 to 10W/m-K, and the package junction temperature compared to the baseline design.

Table 4.  Heatsink Sizes and Flow Conditions
Heatsink Profile Size Profile Flow Condition (Velocity, LFM)
19x19x15 mm Low 0, 200, 400
19x19x23 mm Medium 0, 200, 400
19x19x28 mm High 0, 200, 400

For low-power applications ~1W range the TIM does not play a role, and a low thermal conductivity gap pad is sufficient. For powers in the range of ~5W, using GAP PAD TIMs of medium thermal conductivity from 3 to 4/m-K, significantly enhances thermal performance, which is depicted below for medium profile heatsink. Similar observation holds good for low profile and high profile heatsink types. Beyond this threshold, high-performance TIM materials have only a marginal impact on thermal performance less than 1°C. For these applications, medium conductivity gap pads are typically the preferred choice due to their cost-effectiveness.

Figure 10. Effect of Different TIM Materials on Package Junction Temperature for Low Power Range MAX® 10 FPGA B610 Package Using Medium Profile Heatsink

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