Thermal Design User Guide: MAX® 10 FPGA B610 Package

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ID 851247
Date 5/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines 2. MAX® 10 FPGA B610 Package Mechanical Construction 3. MAX® 10 FPGA B610 Package CTM Construction 4. Quartus Requirements and Power Estimation 5. General FPGA Thermal Design Considerations 6. Thermal Design Process 7. Thermal Solution Mechanical Design 8. Vendor References 9. Document Revision History for the MAX® 10 FPGA B610 Package Thermal Design User Guide A. Thermal Design Elements
1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines x
1.1. Thermal Design Requirements 1.2. Definitions of Thermal and Power Terms Used in this Document
2. MAX® 10 FPGA B610 Package Mechanical Construction x
2.1. Thermal Design Process Flow 2.2. Thermal Resistance Values Summary
3. MAX® 10 FPGA B610 Package CTM Construction x
3.1. CTM File Format 3.2. Thermal Modeling with the CTM 3.3. Obtaining the CTM
4. Quartus Requirements and Power Estimation x
4.1. Board Thermal Model 4.2. QPA Outputs
5. General FPGA Thermal Design Considerations x
5.1. FPGA Power Considerations 5.2. FPGA Maximum Allowed Power Dissipation 5.3. Static, Dynamic, and Standby Power
6. Thermal Design Process x
6.1. Package Heat Flow Path 6.2. Recommended Thermal Design Methodology
7. Thermal Solution Mechanical Design x
7.1. Mechanical Design 7.2. TIM2 Selection 7.3. Summary
7.1. Mechanical Design x
7.1.1. Bond Line Thickness (BLT) 7.1.2. Die Warpage 7.1.3. Package Loading 7.1.4. Recommended Pressure Variation Across the Package
7.2. TIM2 Selection x
7.2.1. Gap Pad TIMs 7.2.2. Gap Pad TIM Thermal Conductivity Data 7.2.3. Parametric Studies with Different TIM Materials
1. Introduction to MAX® 10 FPGA B610 Package Thermal Design Guidelines
2. MAX® 10 FPGA B610 Package Mechanical Construction
3. MAX® 10 FPGA B610 Package CTM Construction
4. Quartus Requirements and Power Estimation
5. General FPGA Thermal Design Considerations
6. Thermal Design Process
7. Thermal Solution Mechanical Design
8. Vendor References
9. Document Revision History for the MAX® 10 FPGA B610 Package Thermal Design User Guide
A. Thermal Design Elements

4.1. Board Thermal Model

The board thermal model has multiple options. If you want the QPA thermal model to take the ӨJB into consideration, set the Board Thermal Model parameter to either JEDEC (2s2p) or Typical Board. Otherwise, set the Board Thermal Model parameter to None (conservative). In this case, the path through the board is not considered for power dissipation and a more conservative thermal power estimate is obtained.

No Heat Sink on Device

In the model used in the QPA, power is dissipated through the case and board, the ӨJA values are calculated for differing airflow options accounting for the paths through the case and through the circuit board.

With Heat Sink on Device

When you use a heat sink, the major paths of power dissipation are from the device through the case, thermal interface material, and heat sink. There is also a path of power dissipation through the circuit board. The path through the board has less impact that the path to air.

In the model used in QPA, power is dissipated through the board or through the case and heat sink. The junction-to-board thermal resistance (ӨJB) refers to the thermal resistance of the path through the circuit board. Junction-to-ambient thermal resistance (ӨJA top) refers to the thermal resistance of the path through the case, thermal interface material, and heat sink.

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