1. Agilex™ 3 Clocking and PLL Overview
2. Agilex™ 3 Clocking and PLL Architecture and Features
3. Agilex™ 3 Clocking and PLL Design Considerations
4. Clock Control Altera™ FPGA IP Core
5. IOPLL FPGA IP
6. I/O PLL Reconfiguration
7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
6.1.1. Release Information for EMIF Calibration IP
6.1.2. Setting Up the IOPLL FPGA IP
6.1.3. Setting Up the EMIF Calibration IP
6.1.4. Connectivity Between IOPLL FPGA IP and EMIF Calibration IP
6.1.5. Axilite Interface Ports in the EMIF Calibration IP
6.1.6. Reconfiguration Guideline for HSIO I/O PLLs
6.1.7. Design Example for HSIO I/O PLL Reconfiguration
6.2.2.1. Read and Write Operations via Avalon® Memory-Mapped Interface
6.2.2.2. Enabling Reconfiguration for The Desired I/O PLL
6.2.2.3. Clearing off Calibration Statuses
6.2.2.4. Reconfiguring The I/O PLL
6.2.2.5. Enabling Recalibration for HVIO PLLs
6.2.2.6. Requesting Recalibration of I/O PLL
6.2.2.7. Clock Gating (Optional)
6.3.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration
Divide Settings | Write Address Bus Setting | Parameter | Write Data Bus Setting | Description |
---|---|---|---|---|
M Counter | 0x40 | Total Count | data [28:20] | Total count for M Counter |
Bypass Enable |
data [31] |
|
||
N Counter | High Count | data [7:0] |
|
|
Low Count | data [16:9] | |||
Odd Division | data [17] |
|
||
Bypass Enable | data [8] |
|
||
Charge Pump Current | 0x44 | Charge Pump Settings | data [15:1] |
|
C- Counters | C0 = 0x5C C1 = 0x60 C2 = 0x64 C3 = 0x68 C4 = 0x6C C5 = 0x70 C6 = 0x74 |
High Count | data [7:0] |
|
Low Count | data [30:23] | |||
Odd Division | data [31] |
|
||
Bypass Enable | data [8] |
|
||
Counter Preset | data [18:11] |
|
||
Phase Mux Preset | data [21:19] |
|
||
Enable Recalibration | 0x48 | Permit Calibration | data [14] |
|
Calibration | 0x88 | Calibration Request | data [11] |
|
Reset | 0x80 | PLL Reset | data [2] |
|
Registers enablement | 0x10 | Enable registers | data [0] |
|
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