Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.3.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration

Table 21.  Divide Settings and Corresponding Address Bus for Reconfiguration
Divide Settings Write Address Bus Setting Parameter Write Data Bus Setting Description
M Counter 0x40 Total Count data [28:20] Total count for M Counter

Bypass Enable

data [31]
  • Data [31] =bypass enable
    • Data [31] =1,bypass is enabled. The counter is bypassed with counter division value = 1.
N Counter High Count data [7:0]
  • Data [7:0] =high_count
  • Data [16:9] =low_count
  • total_count=high_count+low_count
Low Count data [16:9]
Odd Division data [17]
  • Data [17] =Odd division
    • Data [17] =0, odd division is disabled.

      The selected counter duty cycle =

      high_count/total_count.

  • Data [17] =1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable data [8]
  • Data [8] =bypass enable
    • Data [8] =1,bypass is enabled. The counter is bypassed with counter division value = 1.
Charge Pump Current 0x44 Charge Pump Settings data [15:1]
  • Data [15:1]=Charge Pump Setting
    • Configure charge pump setting[15:1]
  • For more information about the Reconfiguration table, refer to the Multiply Factor and The Corresponding Data Bit Setting For Charge Pump Current table
C- Counters

C0 = 0x5C

C1 = 0x60

C2 = 0x64

C3 = 0x68

C4 = 0x6C

C5 = 0x70

C6 = 0x74

High Count data [7:0]
  • Data [7:0] =high_count
  • Data [30:23] =low_count
  • total_count=high_count+low_count
Low Count data [30:23]
Odd Division data [31]
  • Data [31] =Odd division
    • Data [31] =0, odd division is disabled.

      The selected counter duty cycle =

      high_count/total_count.

  • Data [31] =1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable data [8]
  • Data [8] =bypass enable
    • Data [8] =1,bypass is enabled. The counter is bypassed with counter division value = 1.
Counter Preset data [18:11]
  • Sets the number of phase shift steps per dynamic phase shift operation. Valid range is 1 to (C-Counter Divide). Each step equals one I/O PLL VCO clock period. The default value is 1 (no phase shift). To shift by one VCO clock period, set the value to 2, and so on.
Phase Mux Preset data [21:19]
  • Specifies how many phase shifts are applied during each dynamic phase shift operation. Up to 7 steps are supported. Each step equals 1/8 of the I/O PLL VCO period.
Enable Recalibration 0x48 Permit Calibration data [14]
  • Data [14]=Enable recalibration for HVIO I/O PLL
    • Data [14]=1, to enable recalibration
Calibration 0x88 Calibration Request data [11]
  • Data [11]=Request Recalibration
    • Data [11]=1, to request recalibration
Reset 0x80 PLL Reset data [2]
  • Data [2]=Reset PLL
    • Data [2]=1,to reset PLL prior to recalibration request
Registers enablement 0x10 Enable registers data [0]
  • Data [0] = Enable registers of divide settingsfor read-modify-write operation.
    • Data [0]=1,to enable registers for read-modify-write operation prior to reconfiguration.