1. Agilex™ 3 Clocking and PLL Overview
2. Agilex™ 3 Clocking and PLL Architecture and Features
3. Agilex™ 3 Clocking and PLL Design Considerations
4. Clock Control Altera™ FPGA IP Core
5. IOPLL FPGA IP
6. I/O PLL Reconfiguration
7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
6.1.1. Release Information for EMIF Calibration IP
6.1.2. Setting Up the IOPLL FPGA IP
6.1.3. Setting Up the EMIF Calibration IP
6.1.4. Connectivity Between IOPLL FPGA IP and EMIF Calibration IP
6.1.5. Axilite Interface Ports in the EMIF Calibration IP
6.1.6. Reconfiguration Guideline for HSIO I/O PLLs
6.1.7. Design Example for HSIO I/O PLL Reconfiguration
6.2.2.1. Read and Write Operations via Avalon® Memory-Mapped Interface
6.2.2.2. Enabling Reconfiguration for The Desired I/O PLL
6.2.2.3. Clearing off Calibration Statuses
6.2.2.4. Reconfiguring The I/O PLL
6.2.2.5. Enabling Recalibration for HVIO PLLs
6.2.2.6. Requesting Recalibration of I/O PLL
6.2.2.7. Clock Gating (Optional)
6.2.3.1. Reconfiguration Option: Reconfiguration Through EMIF Calibration IP
After the I/O PLL reconfiguration operation is complete, the I/O PLL operates in the following configuration:
- HVIO I/O PLL 1:
- 400 MHz with 0 ps phase shift on counter C1 output
- 400 MHz with phase shift on counter C2 output
The state machine initiates the I/O PLL recalibration process when the I/O PLL reconfiguration operation is complete.
To run the design example, perform these steps:
- Program the device top.sof.
- In the In-System Sources & Probes IP core, assert mode_0 to high and keep mode_1 low.
- Assert start_reconfig signal to start the I/O PLL reconfiguration operation.