Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6. I/O PLL Reconfiguration

Agilex™ 3 devices support phase-locked loop (PLL) reconfiguration and dynamic phase shifting for I/O PLLs, allowing you to adjust PLL settings in real-time while the device operates in user mode. This feature allows changes to PLL divide settings without requiring a full FPGA reconfiguration. The I/O PLL architecture uses divide counters (N, M, and C) and a voltage-controlled oscillator (VCO) to generate the desired output phase and frequency.

Reconfiguration methods vary by block type:

  • HSIO I/O PLLs — Divide settings are reconfigured via the AXI4-Lite interface through the EMIF Calibration IP.
  • HVIO I/O PLLs — Divide settings are reconfigured directly through the reconfiguration ports using the Avalon® memory-mapped interface.

Key capabilities:

  • I/O PLL Reconfiguration
    • Enable dynamic reconfiguration of PLL the dynamic reconfiguration tab of the IOPLL FPGA IP to reconfigure the individual I/O PLL registers. You can also perform dynamic phase shift.
  • Recalibration of the I/O PLL
    • Perform recalibration of the I/O PLL without any reconfiguration.
    • Trigger recalibration if the reference clock frequency changes.
  • I/O PLL clock gating
    • Gate and un-gate I/O PLL output clock 0 to output clock 6 of the I/O PLL.

For all three functions, the reconfiguration operation is controlled by specific data bits stored at designated register addresses. If configuration parameters are set to illegal settings, the I/O PLL may lose lock, causing device reliability issues. Altera recommends following these guidelines strictly:

  • Ensure the configuration setting is a legal value so that the I/O PLL has a legal configuration. To ensure your configuration is legal, refer to the IOPLL IP Core Parameters - Advanced Parameters Tab table for correct settings.
  • If the value you are reconfiguring is only part of the 32-bit register at the specified address in the I/O PLL’s internal memory, perform a read-modify-write operation and make sure you do not overwrite the other bits of the register.
  • After dynamic reconfiguration, manually trigger the recalibration of the I/O PLL, as it is necessary to recalibrate it. You do not need to perform recalibration for clock gating or dynamic phase shift reconfiguration.