Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.1.6.4. Recalibration of I/O PLL

  1. Set the address bus value according to the table below:
    Address Bus Value for HSIO I/O PLL Reconfiguration Value
    s0_axi4lite_awaddr [7:0] 0x88
    s0_axi4lite_awaddr [20:13] I/O PLL Base Address
    s0_axi4lite_awaddr [23:21] 3’b101
  2. Assert bit [11] of the s0_axi4lite_wdata data bus high to initiate recalibration. Asserted lock signal indicates that the recalibration is complete.