Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.2.2.6. Requesting Recalibration of I/O PLL

  1. Set the address bus value according to the table below:
    Address Bus Value for HVIO I/O PLL Reconfiguration Value
    Core_avl_address[8:0] 0x88
  2. Set the data bus value [11] to 1'b1 to initiate recalibration process. Asserted lock signal indicates that the recalibration is complete.