Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

5. IOPLL FPGA IP

The IOPLL FPGA IP allows you to configure the settings of the Agilex™ 3 I/O PLL.

The IOPLL IP supports the following features:

  • Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
  • Generates up to four output clocks for I/O bank I/O PLL and seven output clocks for fabric-feeding I/O PLL for the Agilex™ 3 device.
  • Switches between two reference input clocks.
  • Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL dedicated cascading mode.

The IOPLL IP is available under the Basic Functions > PLL category of the IP Catalog.