Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.1.7.1. Reconfiguration Option: Reconfiguration Through EMIF Calibration IP

After the I/O PLL reconfiguration operation is complete, the I/O PLL operates in the following configuration:

  • HSIO I/O PLL 1:
    1. 400 MHz with 0 ps phase shift on counter C1 output
    2. 400 MHz with 0 ps phase shift on counter C2 output

The state machine initiates the I/O PLL recalibration process when the I/O PLL reconfiguration operation is complete.

To run the design example that reconfigures the divide settings of the I/O PLL, perform these steps:

  1. Program the device top.sof.
  2. In the In-System Sources & Probes IP core, assert mode_0 high and keep mode_1 low.
  3. Assert the reconfig_start signal to start the I/O PLL reconfiguration operation.