1. Agilex™ 3 Clocking and PLL Overview
2. Agilex™ 3 Clocking and PLL Architecture and Features
3. Agilex™ 3 Clocking and PLL Design Considerations
4. Clock Control Altera™ FPGA IP Core
5. IOPLL FPGA IP
6. I/O PLL Reconfiguration
7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Locations
2.2.4. PLL Architecture
2.2.5. PLL Control Signals
2.2.6. PLL Feedback Modes
2.2.7. Clock Multiplication and Division
2.2.8. Programmable Phase Shift
2.2.9. Programmable Duty Cycle
2.2.10. PLL Cascading
2.2.11. PLL Input Clock Switchover
2.2.12. PLL Reconfiguration and Dynamic Phase Shift
2.2.13. PLL Calibration
6.1.1. Release Information for EMIF Calibration IP
6.1.2. Setting Up the IOPLL FPGA IP
6.1.3. Setting Up the EMIF Calibration IP
6.1.4. Connectivity Between IOPLL FPGA IP and EMIF Calibration IP
6.1.5. Axilite Interface Ports in the EMIF Calibration IP
6.1.6. Reconfiguration Guideline for HSIO I/O PLLs
6.1.7. Design Example for HSIO I/O PLL Reconfiguration
6.2.2.1. Read and Write Operations via Avalon® Memory-Mapped Interface
6.2.2.2. Enabling Reconfiguration for The Desired I/O PLL
6.2.2.3. Clearing off Calibration Statuses
6.2.2.4. Reconfiguring The I/O PLL
6.2.2.5. Enabling Recalibration for HVIO PLLs
6.2.2.6. Requesting Recalibration of I/O PLL
6.2.2.7. Clock Gating (Optional)
6.1.7. Design Example for HSIO I/O PLL Reconfiguration
The design example consists of the following device and IPs:
- Uses Agilex™ 3 device to demonstrate the implementation of the following two different HSIO I/O PLL reconfiguration options:
- I/O PLL divide settings reconfiguration
- Clock gating reconfiguration
- Includes the following IPs:
- IOPLL IP
- EMIF Calibration IP
- In-System Sources & Probes IP
- Agilex™ Reset Release IP
You must install Quartus® Prime software version 25.1.1 or later on a Windows* or Linux* computer that meets the minimum requirements.
Before reconfiguration, the I/O PLLs configurations are as follows:
- HSIO Bank I/O PLL 1:
- 50 MHz with 0 ps phase shift on counter C0 output
- 50 MHz with 0 ps phase shift on counter C1 output
The input reference clock is 100 MHz. The EMIF Calibration IP connect to a state machine to perform I/O PLL reconfiguration operations. Assert reconfig_start signal to trigger the operation. . You can select the desired reconfiguration mode through the mode_0 and mode_1 inputs, controlled through the In-System Sources & Probes IP core.
Table 19. Reconfiguration Mode Selection for the Design Example Reconfiguration Mode mode_1 mode_0 Reconfiguration Through EMIF Calibration IP 0 1 Clock gating reconfiguration 1 0 Follow these steps to recompile the design example:
- Download and restore the Design Example file.
- Change the device and pin assignments to match your hardware.
- Recompile the design example and ensure that it does not contain any timing violation after reconfiguration.