Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.2.2.3. Clearing off Calibration Statuses

  1. Set the address bus value for core_avl_address [8:0] according to the table below:
    Address Bus Value for HVIO I/O PLL Reconfiguration Value
    core_avl_address[8:0] 0x58
  2. Set the data bus value of bit [7]and bit [21] to 1’b0.