Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.1.6.3. Reconfiguring The I/O PLL

  1. Set the address bus value according to the table below:
    Table 17.  Reconfiguring The I/O PLL
    Address Bus Value for HSIO I/O PLL Reconfiguration Value
    s0_axi4lite_awaddr [7:0] Divide Settings Address
    s0_axi4lite_awaddr [20:13] I/O PLL Base Address
    s0_axi4lite_awaddr [23:21] 3’b101
  2. Set the address bus value for s0_axi4lite_awaddr [7:0] and the data bus value for s0_axi4lite_wdata[31:0] as the desired PLL setting. For more details about the PLL parameter settings, refer to Address Bus and Data Bus Settings.
  3. After updating the PLL parameter settings, a reset pulse must be issued. To do this, set s0_axi4lite_awaddr[7:0] to the appropriate reset address (0x80) and assert bit [2] of the data bus for at least 10 ns.
  4. After the I/O PLL reconfiguration is complete, you must manually trigger the I/O PLL recalibration.