Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2025.09.17 25.1.1
  • Updated I/O PLL Reconfiguration to separate HSIO and HVIO content.
  • Added the following topics:
    • Design Example for HSIO I/O PLL Reconfiguration
    • Design Example for HVIO I/O PLL Reconfiguration
  • Updated the Address Bus and Data Bus Settings.
2025.04.07 25.1 Initial release.