Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.2.2.4. Reconfiguring The I/O PLL

  1. Set the address bus value for core_avl_address [8:0] and the data bus value as the desired PLL setting. For more details about the PLL parameter settings, refer to Address Bus and Data Bus Settings.
  2. After updating the PLL parameter settings, you must issue a reset pulse. To do this, set core_avl_address[8:0] to the appropriate reset address(0x80) and assert bit [2] of the data bus for at least 10 ns.
  3. After the I/O PLL reconfiguration is complete, you must manually trigger the I/O PLL recalibration.