Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.1.6.2. Clearing off Calibration Statuses

  1. Set the address bus value for s0_axi4lite_awaddr according to the table below:
    Table 16.  Clearing off Calibration Statuses
    Address Bus Value for HSIO I/O PLL Reconfiguration Value
    s0_axi4lite_awaddr [7:0] 0x58
    s0_axi4lite_awaddr [20:13] I/O PLL Base Address
    s0_axi4lite_awaddr [23:21] 3’b101
  2. Set the data bus value of bit [7] and bit [21] to 1’b0.