Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.2.2.5. Enabling Recalibration for HVIO PLLs

  1. Set the address bus value for core_avl_address [8:0] according to the table below:
    Address Bus Value for HVIO I/O PLL Reconfiguration Value
    Core_avl_address[8:0] 0x48
  2. Set the data bus value [14] to 1'b1 prior to initiating the recalibration process.
  3. If your design requires reconfiguring the individual I/O PLL multiple times, be sure to set bit [14] of the data bus to 1'b0 after each recalibration is complete.