Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.2.2.2. Enabling Reconfiguration for The Desired I/O PLL

  1. Set the address bus value for core_avl_address [8:0] according to the table below:
    Address Bus Value for HVIO I/O PLL Reconfiguration Value
    core_avl_address[8:0] 0x10
  2. Set the LSB of data bus value to 1’b1 to enable read and write operation.