Clocking and PLL User Guide: Agilex™ 3 FPGAs and SoCs

ID 847921
Date 9/12/2025
Public
Document Table of Contents

6.2.2.7. Clock Gating (Optional)

  1. Set the address bus value according to the table below:
    Address Bus Value for HVIO I/O PLL Reconfiguration Value
    Core_avl_address[8:0] 0x54
  2. Set the data bus value for [24:18] accordingly.

    For more information about the Reconfiguration table, refer to the Address and Bus Data Settings.