High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 12/04/2023
Public
Document Table of Contents

A.2. Simulating HBM2E User Designs

To run the simulations with your HBM2E designs created using the Intel® Quartus® Prime software flow, you must manually add the RTL simulation registration include file (.inc) in the top-level of your design. The initiator-to-target connectivity and address mapping are not included in the netlist. If you use the Platform Designer flow to make connection between initiators and targets and generate a design, it creates the registration file (.inc) for your design. In this case, you do not need to manually add the registrations statements in the top-level of your design.
You must add one registration statement for each initiator-to-target connection, specifying the start address and the size of that connection’s address range. Refer to the Simulating the NoC Designs section in the Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide for detailed information on how to add NoC connectivity and address mapping to the simulation net list.

The HBM2E Intel® FPGA IP design example creates simulation files with registration statements. You can refer to the registration statements included in the ed_sim.v file generated with the design example. The ed_sim.v file resides at this location: <your_directory>/hbm_fp_0_example_design/sim/ed_sim/sim/ed_sim.v

The following code fragment shows a snapshot of the registration statements for a single-channel design:

.noc_initiator_b256.iniu_0.initiator_inst_0.register_if(ed_sim.hbm_fp_0.hbm_fp_0.tniu_ch0_u0.target_0.target_inst_0.get_if() , 0, 31'h40000000);
.noc_initiator_b256.iniu_1.initiator_inst_0.register_if(ed_sim.hbm_fp_0.hbm_fp_0.tniu_ch0_u1.target_0.target_inst_0.get_if() , 0, 31'h40000000);
.noc_initiator_b256.iniu_0.initiator_inst_0.register_if(ed_sim.hbm_fp_0.hbm_fp_0.tniu_ch0_ch1_sb.target_0.target_lite_inst_0.target_inst_0.get_if() , 44'h40000000, 31'h8000000);