High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 12/04/2023
Public
Document Table of Contents

4.2.3. Modifying Your Pin Assignments to Choose the Physical Location of the HBM2E Device

There are two HBM2E memory devices in Intel Agilex® 7 M-Series FPGAs. One HBM2E memory is on the top of the FPGA and the other is on the bottom. With the Intel® HBM2E FPGA IP you must add the assignments in your qsf file to choose the location of the HBM2e device.

You can choose top versus bottom device by specifying the pin assignment for the dedicated refclk pins for the UIB PLL and the NoC PLL.

Modify your qsf file with the following assignments to use top or bottom location of the HBM2e memory device:

Specifying the top HBM

To specify the top HBM, set these assignments:

Set_location_assignment PIN_AR36 -to uibpll_refclk_clk
Set_location_assignment PIN_AN36 -to "uibpll_refclk_clk(n)"
Set_location_assignment PIN_AU52 -to noc_clk_ctrl_refclk_clk

Specifying the bottom HBM

To specify the bottom HBM, set these assignments:

Set_location_assignment PIN_EC36 -to uibpll_refclk_clk
Set_location_assignment PIN_ED35 -to "uibpll_refclk_clk(n)"
Set_location_assignment PIN_EE56 -to noc_clk_ctrl_refclk_clk